Dear all,
I would like to ask for help, first trying to understand the source of the problem and then to solve it.
I'm having a problem with the reported clock value of the JESD204 link frequency value of an ad9081-fmca using a ZCU102 carrier board, running the kuiper linux provided by AD.
I've generated the project with:
make JESD_MODE=8B10B RX_RATE=5 TX_RATE=10 RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=1 RX_JESD_F=2 RX_JESD_NP=16 TX_JESD_M=4 TX_JESD_L=4 TX_JESD_S=1 TX_JESD_F=2 TX_JESD_NP=16
Before running the make I changed the timing constraints file according to the frequencies resulting of the mode and lane rates, fpga_refclk_in = 500 MHz, rx_device_clk = 125 MHz and tx_device_clk = 250 MHz.
This is the part of the constraint file for the definition of the clocks:
# Primary clock definitions
create_clock -period 2 -name refclk [get_ports fpga_refclk_in_p]
# device clock
create_clock -period 4 -name tx_device_clk [get_ports clkin6_p]
create_clock -period 8 -name rx_device_clk [get_ports clkin10_p]
# Constraint SYSREFs
# Assumption is that REFCLK and SYSREF have similar propagation delay,
# and the SYSREF is a source synchronous Edge-Aligned signal to REFCLK
set_input_delay -clock [get_clocks tx_device_clk] 4 [get_ports sysref2_*]
The frequency values were also updated into the device tree.
This is the output of the jesd_status command:
Here it appears the first error/warning, the measured value of the rx link clock is different from the one it should be.
Then, if I search for the reported clocks I see:
cat /sys/kernel/debug/clk/clk_summary
enable prepare protect duty
clock count count count rate accuracy phase cycle nshot
----------------------------------------------------------------------------------------------------
clkin2_0 0 0 0 0 0 0 50000 0
clkin1_0 0 0 0 0 0 0 50000 0
si570_mgt 0 0 0 148499999 0 0 50000 0
si570_user 0 0 0 299999997 0 0 50000 0
hmc7044_out13 0 0 0 1953125 0 0 50000 0
hmc7044_out12 4 4 2 500000000 0 0 50000 0
tx_out_clk 0 0 0 250000000 0 0 50000 0
tx_gt_clk 1 1 1 10000000 0 0 50000 0
rx_out_clk 0 0 0 250000000 0 0 50000 0
rx_gt_clk 1 1 1 5000000 0 0 50000 0
hmc7044_out10 1 1 0 125000000 0 0 50000 0
hmc7044_out6 1 1 0 250000000 0 0 50000 0
hmc7044_out3 0 0 0 1953125 0 0 50000 0
hmc7044_out2 2 2 0 500000000 0 0 50000 0
I couldn't understand if the meaasured link clock os correctly measured or if we are making something wrong here with the parameters we included into the make.
The values were generated with the JESD mode tool.
If I change the PL plclk0 frequency from 100MH to 150 MHz, the reported values are these:
Then, making from the clock summary output I see this:
cat /sys/kernel/debug/clk/clk_summary
enable prepare protect duty
clock count count count rate accuracy phase cycle nshot
----------------------------------------------------------------------------------------------------------------------------------
clkin2_0 0 0 0 0 0 0 50000 0
clkin1_0 0 0 0 0 0 0 50000 0
si570_mgt 0 0 0 148499999 0 0 50000 0
si570_user 0 0 0 299999997 0 0 50000 0
hmc7044_out13 0 0 0 1953125 0 0 50000 0
hmc7044_out12 4 4 2 500000000 0 0 50000 0
tx_out_clk 0 0 0 250000000 0 0 50000 0
tx_gt_clk 1 1 1 10000000 0 0 50000 0
rx_out_clk 0 0 0 250000000 0 0 50000 0
rx_gt_clk 1 1 1 5000000 0 0 50000 0
hmc7044_out10 1 1 0 125000000 0 0 50000 0
hmc7044_out6 1 1 0 250000000 0 0 50000 0
hmc7044_out3 0 0 0 1953125 0 0 50000 0
hmc7044_out2 2 2 0 250000000 0 0 50000 0
1_ I would like to understand first, why the reported values are different if I didn't change the frequency values of the HMC7044.
2_ Then, how do I fix this problem?
3_ Is it any guide about how the scripts configure all the internal parameters of the JESD204 interfaces?
4_ Not related to this, but how can I select the internal PBRS generator?
Thank you in advance!
