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ad9081-fmca-ebz + ZCU102, Measured Link Clock has a wrong value

Category: Hardware
Product Number: zcu102

Dear all, 

I would like to ask for help, first trying to understand the source of the problem and then to solve it.

I'm having a problem with the reported clock value of the JESD204 link frequency value of an ad9081-fmca using a ZCU102 carrier board, running the kuiper linux provided by AD.

I've generated the project with:

make JESD_MODE=8B10B RX_RATE=5 TX_RATE=10 RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=1 RX_JESD_F=2 RX_JESD_NP=16 TX_JESD_M=4 TX_JESD_L=4 TX_JESD_S=1 TX_JESD_F=2 TX_JESD_NP=16

Before running the make I changed the timing constraints file according to the frequencies resulting of the mode and lane rates, fpga_refclk_in = 500 MHz, rx_device_clk = 125 MHz and tx_device_clk = 250 MHz.

This is the part of the constraint file for the definition of the clocks:

# Primary clock definitions
create_clock -period 2 -name refclk [get_ports fpga_refclk_in_p]

# device clock
create_clock -period 4 -name tx_device_clk [get_ports clkin6_p]
create_clock -period 8 -name rx_device_clk [get_ports clkin10_p]


# Constraint SYSREFs
# Assumption is that REFCLK and SYSREF have similar propagation delay,
# and the SYSREF is a source synchronous Edge-Aligned signal to REFCLK
set_input_delay -clock [get_clocks tx_device_clk] 4 [get_ports sysref2_*]

The frequency values were also updated into the device tree.

This is the output of the jesd_status command:

   

Here it appears the first error/warning, the measured value of the rx link clock is different from the one it should be.

Then, if I search for the reported clocks I see:

cat /sys/kernel/debug/clk/clk_summary

                 enable    prepare    protect                                   duty
clock            count     count      count      rate   accuracy     phase     cycle       nshot
----------------------------------------------------------------------------------------------------
clkin2_0          0        0          0          0          0          0        50000        0
clkin1_0          0        0          0          0          0          0        50000        0
si570_mgt         0        0          0          148499999  0          0        50000        0
si570_user        0        0          0          299999997  0          0        50000        0
hmc7044_out13     0        0          0          1953125    0          0        50000        0
hmc7044_out12     4        4          2          500000000  0          0        50000        0
tx_out_clk        0        0          0          250000000  0          0        50000        0
tx_gt_clk         1        1          1          10000000   0          0        50000        0
rx_out_clk        0        0          0          250000000  0          0        50000        0
rx_gt_clk         1        1          1          5000000    0          0        50000        0
hmc7044_out10     1        1          0          125000000  0          0        50000        0
hmc7044_out6      1        1          0          250000000  0          0        50000        0
hmc7044_out3      0        0          0          1953125    0          0        50000        0
hmc7044_out2      2        2          0          500000000  0          0        50000        0

I couldn't understand if the meaasured link clock os correctly measured or if we are making something wrong here with the parameters we included into the make.

The values were generated with the JESD mode tool.

If I change the PL plclk0 frequency from 100MH to 150 MHz, the reported values are these:

   

Then, making from the clock summary output I see this:

cat /sys/kernel/debug/clk/clk_summary

                                      enable       prepare      protect                                              duty
clock                                 count        count        count          rate        accuracy    phase         cycle    nshot
----------------------------------------------------------------------------------------------------------------------------------
clkin2_0                                0            0              0            0           0             0         50000         0
clkin1_0                                0            0              0            0           0             0         50000         0
si570_mgt                               0            0              0            148499999   0             0         50000         0
si570_user                              0            0              0            299999997   0             0         50000         0
hmc7044_out13                           0            0              0            1953125     0             0         50000         0
hmc7044_out12                           4            4              2            500000000   0             0         50000         0
     tx_out_clk                         0            0              0            250000000   0             0         50000         0
     tx_gt_clk                          1            1              1            10000000    0             0         50000         0
     rx_out_clk                         0            0              0            250000000   0             0         50000         0
     rx_gt_clk                          1            1              1            5000000     0             0         50000         0
hmc7044_out10                           1            1              0            125000000   0             0         50000         0
hmc7044_out6                            1            1              0            250000000   0             0         50000         0
hmc7044_out3                            0            0              0            1953125     0             0         50000         0
hmc7044_out2                            2            2              0            250000000   0             0         50000         0

1_ I would like to understand first, why the reported values are different if I didn't change the frequency values of the HMC7044.

2_ Then, how do I fix this problem?

3_ Is it any guide about how the scripts configure all the internal parameters of the JESD204 interfaces?

4_ Not related to this, but how can I select the internal PBRS generator?

Thank you in advance! 

  • Hi,

    At a quick glance, I noticed some things. I will come back later with a more detailed response for your theoretical questions.

    But first, I see you wrote RX_LANE and not RX_LANE_RATE. Same for TX. This way, our tool doesn't know of this parameter so it takes the default values for the lane rates, meaning these: https://github.com/analogdevicesinc/hdl/blob/main/projects/ad9081_fmca_ebz/zcu102/system_project.tcl#L35-L36

    Another thing is, the F parameter. Even if you set it, the tool doesn't take it into consideration, because it is calculated in the background. So I would remove these parameters from the command, as it just makes the folder name longer.

    Can you try again with these recommendations?

    Best regards,
    Iulia

  • Hi Iulia, 

    Thanks for your answer.

    I tried again with your recommendations, the output for the jesd_status is still as follows:

      

    If I change in the PS the PL0 clock to 150 MHz:

      

    Regards,

    Bruno

  • Can you share with me the changes you did in the dts?

    3_ Is it any guide about how the scripts configure all the internal parameters of the JESD204 interfaces?

    Sadly, we don't have.

    4_ Not related to this, but how can I select the internal PBRS generator?

    Are you referring to this one maybe? https://analogdevicesinc.github.io/hdl/library/axi_adxcvr/index.html#physical-layer-prbs-testing 

  • Sure! I include here only the lines we modified:

    ...
            adi,pll2-output-frequency = <3000000000>;
    ...
            hmc7044_c6: channel@6 {
                reg = <6>;
                adi,extended-name = "CORE_CLK_TX";
                adi,divider = <12>;                                 // 250 MHz (Lane Rate/40)
                adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
            };
            hmc7044_c10: channel@10 {
                reg = <10>;
                adi,extended-name = "CORE_CLK_RX_ALT";
                adi,divider = <24>;                                 // 125 MHz (Lane Rate/40)
                adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
            };
            hmc7044_c12: channel@12 {
                reg = <12>;
                adi,extended-name = "FPGA_REFCLK2";
                adi,divider = <6>;                                  // 500 MHz (Lane Rate/20)
                adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
            };
    ...
                adi,dac-frequency-hz = /bits/ 64 <8000000000>;
    ...
                adi,channelizer-paths {
                    #address-cells = <1>;
                    #size-cells = <0>;
                    adi,interpolation = <2>;
    ...
                adi,jesd-links {
                    #size-cells = <0>;
                    #address-cells = <1>;

                    ad9081_tx_jesd_l0: link@0 {
                        #address-cells = <1>;
                        #size-cells = <0>;
                        reg = <0>;

                        adi,logical-lane-mapping = /bits/ 8 <0 2 7 7 1 7 7 3>;

                        adi,link-mode = <10>;               /* JESD Quick Configuration Mode */
                        adi,subclass = <1>;                 /* JESD SUBCLASS 0,1,2 */
                        adi,version = <1>;                  /* JESD VERSION 0=204A,1=204B,2=204C */
                        adi,dual-link = <0>;                /* JESD Dual Link Mode */

                        adi,converters-per-device = <4>;    /* JESD M */
                        adi,octets-per-frame = <2>;         /* JESD F */

                        adi,frames-per-multiframe = <32>;   /* JESD K */
                        adi,converter-resolution = <16>;    /* JESD N */
                        adi,bits-per-sample = <16>;         /* JESD NP' */
                        adi,control-bits-per-sample = <0>;  /* JESD CS */
                        adi,lanes-per-device = <4>;         /* JESD L */
                        adi,samples-per-converter-per-frame = <1>; /* JESD S */
                        adi,high-density = <0>;             /* JESD HD */
                        adi,tpl-phase-adjust = <3>;
                    };
    ...

                adi,adc-frequency-hz = /bits/ 64 <4000000000>;
                    ad9081_adc0: adc@0 {
                        reg = <0>;
                        adi,decimation = <4>;
                        adi,nco-frequency-shift-hz =  /bits/ 64 <400000000>;
                        adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
                        //adi,crossbar-select = <&ad9081_rx_fddc_chan0>, <&ad9081_rx_fddc_chan2>; /* Static for now */
                    };
                    ad9081_adc1: adc@1 {
                        reg = <1>;
                        adi,decimation = <4>;
                        adi,nco-frequency-shift-hz =  /bits/ 64 <(-400000000)>;
                        adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
                        //adi,crossbar-select = <&ad9081_rx_fddc_chan1>, <&ad9081_rx_fddc_chan3>; /* Static for now */
                    };
                    ad9081_rx_fddc_chan0: channel@0 {
                        reg = <0>;
                        adi,decimation = <4>;
                        adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
                        adi,nco-frequency-shift-hz =  /bits/ 64 <0>;

                    };
                    ad9081_rx_fddc_chan1: channel@1 {
                        reg = <1>;
                        adi,decimation = <4>;
                        adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
                        adi,nco-frequency-shift-hz =  /bits/ 64 <0>;

                    };
    ...
                    ad9081_rx_jesd_l0: link@0 {
                        reg = <0>;
                        adi,converter-select =
                            <&ad9081_rx_fddc_chan0 FDDC_I>, <&ad9081_rx_fddc_chan0 FDDC_Q>,
                            <&ad9081_rx_fddc_chan1 FDDC_I>, <&ad9081_rx_fddc_chan1 FDDC_Q>; // Attention to SEMICOLON
                            // <&ad9081_rx_fddc_chan4 FDDC_I>, <&ad9081_rx_fddc_chan4 FDDC_Q>,
                            // <&ad9081_rx_fddc_chan5 FDDC_I>, <&ad9081_rx_fddc_chan5 FDDC_Q>;

                        adi,logical-lane-mapping = /bits/ 8 <2 0 7 7 7 7 3 1>;

                        adi,link-mode = <11>;               /* JESD Quick Configuration Mode */
                        adi,subclass = <1>;                 /* JESD SUBCLASS 0,1,2 */
                        adi,version = <1>;                  /* JESD VERSION 0=204A,1=204B,2=204C */
                        adi,dual-link = <0>;                /* JESD Dual Link Mode */

                        adi,converters-per-device = <4>;    /* JESD M */
                        adi,octets-per-frame = <2>;         /* JESD F */

                        adi,frames-per-multiframe = <32>;   /* JESD K */
                        adi,converter-resolution = <16>;    /* JESD N */
                        adi,bits-per-sample = <16>;         /* JESD NP' */
                        adi,control-bits-per-sample = <0>;  /* JESD CS */
                        adi,lanes-per-device = <4>;         /* JESD L */
                        adi,samples-per-converter-per-frame = <1>; /* JESD S */
                        adi,high-density = <0>;             /* JESD HD */
                    };
  • Hello Iulia, 

    Any news about the issue?

    Sorry I didn't reply about the PRBS generator. In fact I was referring to this other PRBS, https://analogdevicesinc.github.io/hdl/library/common/ad_dds/index.html#ad-dds. That, I understand is not the same provided to test the link, let me know if I'm wrong.

    Instead of using the DDS input I would like to use the PRBS one.

    Thank you in advance and good start of the week!

    Bruno

  • +1
    •  Analog Employees 
    •  Super User 
    in reply to bvalinot

    Apologies for the delayed reply, I got caught up with other threads and I forgot to reply.

    The modules which report clocks, are doing that by comparing them with the the AXI clock, and if the AXI clock frequency changes in HDL but in software not, then it cannot report the clock properly. Thus changes need to be done in the dts. I checked yours and it should be ok, though I am not sure why it's not working, so I'll investigate more. In the meantime, could you try setting the frequency in IIO Oscilloscope and see if it changes anything?

    Instead of using the DDS input I would like to use the PRBS one.

    This you can do by setting the DAC_DDS_SEL register (see here, DAC channel section, REG_CHAN_CNTRL_7: 0x418). We have only PN7 and PN15, and their inverted versions. 0x418 for the first channel, 0x458, 0x498...

    Or, if you want the terminal version and not to use IIO Osc.: The address to which you should write that value, is constituted like this: the address of the tx_mxfe_tpl_core + 0x4000_0000 + 0x418 = 0x84B1_0418. This is for the first channel. For each channel, you add 0x40.

    In the terminal connected to your board, you should do like (for first channel, voltage0_i is called in IIO Osc.) busybox devmem 0x84B10418 32 to first read the value, and then busybox devmem 0x84B10418 32 0x6 to select PN7 for example.

  • pay attention to the sys_clk frequency on the board or your block design.

  • Hi! What do you mean with the sys_clk frequency? There are several clock sources into the design. 

    Thank you in advance!