Hello, I need to synchronize the ADRV9009 RX sampling clock with an external provided 10-MHz reference clock (PPS aligned reference clock source) on a ADRV9009-ZU11EG RF/ADRV2CRR-FMC based system.
Using the approach described in https://ez.analog.com/fpga/f/q-a/539645/using-pps-adrv9009-zu11eg-on-adrv2crr-fmc I get the AD9545 reporting a successfully lock on the 10-MHz reference clock provided on J4 of the ADRV2CRR-FMC carrier board:
>cat /sys/kernel/debug/clk/Ref-A-Div/Ref-A-Div
Ref-A-Div:
Reference: Valid
>cat /sys/kernel/debug/clk/PLL0/PLL0
PLL0:
PLL status: Locked
Freerun Mode: Off
Holdover Mode: Off
PLL Profile: On
Profile Number: 1
Temperature: 54 C
The AD9545 output OUT0_A_P/N is connected to CLKIN0/RFSYNCIN/CLKIN0/RFSYNCIN_N of the HMC7044 on the carrier board.
Reading https://wiki.analog.com/resources/eval/user-guides/adrv9009-zu11eg/hardware it is clear that the HMC7044 on the carrier board is responsible for the alignment of the reference clock with an external reference.
On https://wiki.analog.com/_media/resources/eval/user-guides/adrv9009-zu11eg/adrv9009_rfsom_clocking_tree.png on the path between the AD9545 and the HMC7044, there is the mention of jumpers R257 and R260 (strange since jumpers are usually indicated using the letter J) and the wire between the two ICs is showed as a dotted wire (suggesting that this is somehow optional)...
On the schematic of ADRV2CRR-FMC R257 and R260 (which are resistors and not jumpers) are on the Expansion header ... I therefore guess they have nothing to do with the clocking system.
On my system I implemented a free running programmable counter clocked by the ADRV9009 RX sampling clock. This programmable counter has a phase alignment mechanism which allows me to re-phase the counter in order to align to the 1-PPS signal used to synchronize the 10 MHz reference clock source. The overflow of such counter generates a pulse winch I connected to an external accessible SMA.
By programming the counter with an overflow value of 245.76e6 (default ADRV9009 RX sampling frequency), I expect the generated pulse (measurable on the previously mentioned SMA) to have a stable phase relationship with the reference 10-MHz (which is phase aligned to a PPS signal).
Unfortunately this is not the case. The counter generated pulse is aligning to the PPS signal when I request to do it, but it then "rapidly" drift's away from the PPS rising edge (the drift direction deepens on the system temperature)... This suggests me that the ADRV9009 RX sampling clock is not aligned or phase locked on the 10 MHz reference clock provided on J4.
Is there anything I need to do, other than modifying the DT in order to have the AD9545 locking on the J4 10 MHz, in order to align/lock the ADRV9009 RX sampling clock to the 10-MHz signal on J4 (ex. adding some stuff to the hmc7044_car DT node)?
What about the jumpers R257/260 mentioned in picture adrv9009_rfsom_clocking_tree.png ?
On https://wiki.analog.com/resources/eval/user-guides/adrv9009-zu11eg ADI i stating:
"For Clock Distribution Synchronization some passive components need to be changed on the ADRV2CRR-FMC Carrier Board.
Rev C (our case):
-
Replace C18, C19, C236, C240 with 0 Ohm resistors
-
Replace C289, C290 with 0 Ohm resistors
-
Unload 0 Ohm resistors from location R77, R112 and insert to R110, R111"
This refers to the case when user wants to use the RFSync from J5/J6 (isn't it ?). As mentioned before, in our case (ADRV2CRR-FMC + one single ADRV9009-ZU11EG) we want to use RefClk generated by the AD9545... what are the components we need to replace ?
Is there any modification we need to apply to the DeviceTree in order to make the system work properly using the RefClock coming from AD9545 ?
Many thanks for any input...
Joel
Corrected RefClock into RFSync
[edited by: Joebre at 9:14 AM (GMT -4) on 4 Jun 2024]
