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ADRV9009-ZU11EG/ADRV2CRR-FMC RF synchronization with 10 MHz/ 1 PPS external reference clock

Category: Hardware
Product Number: ADRV9009-ZU11EG RF, ADRV9009, ADRV9009, ADRV9009, ADRV9009, ADRV9009

Hello, I need to synchronize the ADRV9009 RX sampling clock with an external provided 10-MHz reference clock (PPS aligned reference clock source) on a ADRV9009-ZU11EG RF/ADRV2CRR-FMC based system.

Using the approach described in https://ez.analog.com/fpga/f/q-a/539645/using-pps-adrv9009-zu11eg-on-adrv2crr-fmc I get the AD9545 reporting a successfully lock on the 10-MHz reference clock provided on J4 of the ADRV2CRR-FMC carrier board:

>cat /sys/kernel/debug/clk/Ref-A-Div/Ref-A-Div
Ref-A-Div:
Reference: Valid

>cat /sys/kernel/debug/clk/PLL0/PLL0
PLL0:
PLL status: Locked
Freerun Mode: Off
Holdover Mode: Off
PLL Profile: On
Profile Number: 1
Temperature: 54 C

The AD9545 output OUT0_A_P/N is connected to CLKIN0/RFSYNCIN/CLKIN0/RFSYNCIN_N of the HMC7044 on the carrier board.

Reading https://wiki.analog.com/resources/eval/user-guides/adrv9009-zu11eg/hardware it is clear that the HMC7044 on the carrier board is responsible for the alignment of the reference clock with an external reference.

On https://wiki.analog.com/_media/resources/eval/user-guides/adrv9009-zu11eg/adrv9009_rfsom_clocking_tree.png on the path between the AD9545 and the HMC7044, there is the mention of jumpers R257 and R260 (strange since jumpers are usually indicated using the letter J) and the wire between the two ICs is showed as a dotted wire (suggesting that this is somehow optional)...

On the schematic of ADRV2CRR-FMC R257 and R260 (which are resistors and not jumpers) are on the Expansion header ... I therefore guess they have nothing to do with the clocking system.

On my system I implemented a free running programmable counter clocked by the ADRV9009 RX sampling clock. This programmable counter has a phase alignment mechanism which allows me to re-phase the counter in order to align to the 1-PPS signal used to synchronize the 10 MHz reference clock source. The overflow of such counter generates a pulse winch I connected to an external accessible SMA.

By programming the counter with an overflow value of 245.76e6 (default ADRV9009 RX sampling frequency), I expect the generated pulse (measurable on the previously mentioned SMA) to have a stable phase relationship with the reference 10-MHz (which is phase aligned to a PPS signal).

Unfortunately this is not the case. The counter generated pulse is aligning to the PPS signal when I request to do it,  but it then "rapidly" drift's away from the PPS rising edge (the drift direction deepens on the system temperature)... This suggests me that the ADRV9009 RX sampling clock is not aligned or phase locked on the 10 MHz reference clock  provided on J4.

Is there anything I need to do, other than modifying the DT in order to have the AD9545 locking on the J4 10 MHz, in order to align/lock the ADRV9009 RX sampling clock to the 10-MHz signal on J4 (ex. adding some stuff to the hmc7044_car DT node)?

What about the jumpers R257/260 mentioned in picture adrv9009_rfsom_clocking_tree.png ?

On https://wiki.analog.com/resources/eval/user-guides/adrv9009-zu11eg ADI i stating:

"For Clock Distribution Synchronization some passive components need to be changed on the ADRV2CRR-FMC Carrier Board.

Rev C (our case):

  • Replace C18, C19, C236, C240 with 0 Ohm resistors
  • Replace C289, C290 with 0 Ohm resistors
  • Unload 0 Ohm resistors from location R77, R112 and insert to R110, R111
    "

This refers to the case when user wants to use the RFSync from J5/J6 (isn't it ?). As mentioned before, in our case (ADRV2CRR-FMC  + one single ADRV9009-ZU11EG) we want to use RefClk generated by the AD9545... what are the components we need to replace ?

Is there any modification we need to apply to the DeviceTree in order to make the system work properly using the RefClock coming from AD9545 ?

Many thanks for any input...

Joel



Corrected RefClock into RFSync
[edited by: Joebre at 9:14 AM (GMT -4) on 4 Jun 2024]
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  • Actually, AD9545 has not been implemented in this ADRV9009, and it's not found in the dts either, so I don't expect this to work...

    If you want 1pps, you would need a AD-SYNCHRONA and from this to give the reference on to the carrier. With this type of setup we can help you.

  • Hello Iulia, we adopted ADRV9009-ZU11EG/ADRV2CRR-FMC on our application because ADI is selling it as capable to synchronize to 1PPS (using the ADRV2CRR-FMC 1PPS input), see : https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/adrv2crr-fmc.html#eb-overview (System clocking inputs: EXT REFCLK, SYNC In, 1PPS).

    As mentioned previously, we were able to make AD9545 to lock properly both on 1PPS or 10-MHz reference (https://ez.analog.com/fpga/f/q-a/539645/using-pps-adrv9009-zu11eg-on-adrv2crr-fmc).

    I verified the ADRV2CRR-FMC with the schematics (ver C) and it seems that it is already configured (o ohm resistors) to connect AD9549 output to HMC7044 clk0/rfsync input ... Now I need ADIs help to make the use of the reference coming from AD9545 to synchronize HMC7044 (getting the ADRV2CRR-FMC functionality currently sold by ADI).

    Please help me to make the 1PPS synchronization working properly (i guess it is just a matter of adapting the DT HMC7044 node and maybe some assembly option like soldering or removing a resistor). The use of an external synchronization 1PPS/10-MHz is not feasible in our application (since internal 1PPS/10-MHz synchronization was a requirement of out costumer and we can't at this point redesign part of the system).

    Please help us to make the 1 PPS synchronization feature of ADRV2CRR-FMC working properly.

    Regards, Joel

  • 0
    •  Analog Employees 
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    in reply to Joebre

    Hi Joel,

    I contacted someone from the hardware team and that was the info they provided until they can have a more in-depth look at your thread. Hopefully I will receive an answer today, but if not, I'll ask again early next week. Thank you for your patience.

    Best regards,
    Iulia 

  • Hi Joel,

    As Iulia mentioned earlier the 1 pps synchronization has not been validated. Currently there is no software support and we don't have a clear timeline when this is going to be complete.

    From the hardware point of view to be able to sync to 1pps following modifications are required:

    On ADRV2CRR-FMC:

    • Replace C18, C19, C236, C240 with 0 Ohm resistors
    • Unload R110, R111, load R77, R112
    • Replace C181, C182 with 0 Ohm resistors

    Please note that the system will run in clock distribution. The only difference is that the RFSYNC is fed from the AD9545 instead of J5, J6.

    Again, please note this hasn't been tested. Currently we support the 1pps synchronization through AD-SYNCHRONA.

    Best regards,

    Claudia

  • Hello, thanks for the answer. Considering what you're stating I would suggest you to remove 1PPS clock input from the features listed on the adrv2crr-fmc webpage (https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/adrv2crr-fmc.html#eb-overview) which clearly states that 1 PPS is a clock input option without any note or warning ! This would probably avoid to other peoples to run into the same troubles (as mentioned external synchronization is not an option for our case).

    I need now somehow to get this feature to work even if it has just been sold but never tested.

    As far as I understood using the both RFSYNC input (J5/6) and RFSYNC generated using AD9545 requires to move from a Reference Distribution scheme to a Clock Distribution scheme... is this correct ?

    Is it also correct to assume that by default, as shipped by ADI, the rev C adrv2crr-fmc and ADRV9009-ZU11EG are coming configured with a reference distribution scheme ?

    Is there any additional stuff I need to do for passing from a reference distribution to a clock distribution (ex change the HMC7044 device tree nodes)?

    Do you have any example on how to reconfigure the system to pass from a reference distribution scheme  to a clock distribution one ?

    Regards, Joel

Reply
  • Hello, thanks for the answer. Considering what you're stating I would suggest you to remove 1PPS clock input from the features listed on the adrv2crr-fmc webpage (https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/adrv2crr-fmc.html#eb-overview) which clearly states that 1 PPS is a clock input option without any note or warning ! This would probably avoid to other peoples to run into the same troubles (as mentioned external synchronization is not an option for our case).

    I need now somehow to get this feature to work even if it has just been sold but never tested.

    As far as I understood using the both RFSYNC input (J5/6) and RFSYNC generated using AD9545 requires to move from a Reference Distribution scheme to a Clock Distribution scheme... is this correct ?

    Is it also correct to assume that by default, as shipped by ADI, the rev C adrv2crr-fmc and ADRV9009-ZU11EG are coming configured with a reference distribution scheme ?

    Is there any additional stuff I need to do for passing from a reference distribution to a clock distribution (ex change the HMC7044 device tree nodes)?

    Do you have any example on how to reconfigure the system to pass from a reference distribution scheme  to a clock distribution one ?

    Regards, Joel

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  • Hi Joebre,

    If your application requires to phase lock to an external 1 pps your statement is correct, you need to configure your system in Clock Distribution. Please check the following link, Hardware Design Details chapter.

    https://wiki.analog.com/resources/eval/user-guides/adrv9009-zu11eg

    With the only difference that you need to discharge the last bullet and keep R77 and R112 loaded to use the AD9545 output.

    Please note that the AD9545 output is used by the HMC7044 to phase lock its outputs. An important detail I haven't mentioned so far is that for frequency lock you need to supply a reference clock to J1 and J2 that is already phase locked to 1pps. 

    Here is an example of clock distribution. The example uses Clock Distribution in a system comprised of ADRV9009-ZU11EGAD-FMCOMMS8-EBZ and ADRV2CRR-FMC

    https://github.com/analogdevicesinc/linux/blob/main/arch/arm64/boot/dts/xilinx/zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-sync-fmcomms8-jesd204-fsm-using-clockdist.dts

    Best Regards,

    Claudia

  • Hello, many thanks for the input... in the meanwhile I already found the clockdist.dts you're mentioning above...

    I'm now a bit confused about the statement regarding the fact that for having a frequency lock between the HMC7044  output and the 1 PPS I need to provide a 1PPS synchronized reference clock to the  HMC7044. Just one line above you're stating that the HMC7044  uses the AD9545 output to phase lock it's output... if the output is phase locked to a signal which is phase aligned to a 1PPS signal, it is by definition also frequency locked to it ...

    Hence if the HMC7044 is phase locked to a 1PPS signal it is also frequency locked to it.

    Isn't it ?

    Joel

  • Hi Joebre,

    I would recommend checking out the datasheet for the HMC7043. The HMC7043 it's the same as the HMC7044 configured in Clock distribution. 

    https://www.analog.com/media/en/technical-documentation/data-sheets/HMC7043.pdf

    It will provide more information about the operation of RFSYNC_P/N (equivalent to CLKIN0/RFSYNC on HMC7044) and CLKIN_P/N (equivalent to CLKIN1/FIN on HMC7044) inputs. 

    Best Regards,

    Claudia

  • Hi Caludia, considering the HMC7043 DS, it is not possible lock the ADR9009 sampling clock phase with a 1 PPS signal using the 1PPS input of DRV2CRR-FMC alone. The switch to clock distribution scheme is useless..

    This is true as long as AD9545 is used to generate the RFsync signal, although looking at the AD-SYNCHRONA14-EBZ, it seems definitively possible to use the AD9545 to generate the 38.4 MHz reference clock (phase locked to the 1 PPS signal or 10 MHz). Would this be possible apply this concept also in the ADRV9009-ZY11EG/ADRV-FMC scenario? if not, why ?

    I mean using the AD9545 as 1PPS aligned reference clock generator which provides the reference clock to the  HMC7044 instead of the currently used TCXO (using the reference clock distribution scheme).

    The main difference I see between SYNCHRONA14  and ADRV-FMC is that the HMC7044 of AD-SYNCHRONA14 gets the PPS synchronized reference clock on CLKIN2 instead of CLKIN0 and the presence of a 50 MHz OCX0 connected to M2 pin of the AD9545 (which in the ADRV-FMC board is used for initialization EEPROM i2c clock).

    Is there any reason for which this is not possible in the ADRV9009-ZY11EG/ADRV-FMC  ?

    In the meanwhile I was able to check that AD9545 is properly locking on the reference applied to Ref-A input and generates the requested reference clock on OUT0_A_P/N output.

    Out diff circuit

    The lock of AD9545 on the 10 MHz reference input seems to be stable and continuous....

    As shown in the above picture, the output network of ASRV2CRR-FMC is identical to the one of the one of Synchrona-14... I verified that the nodes/components marked as DNI are not fitted. The differential reference clock generated by AD9545 can clearly been measured on C181 and C182 (30.72 MHz)

    The HMC7044 switches to CLKIN0 (which is connected to the reference clock coming from AD9545) but unfortunately it si not able to lock on it:

    The ASRV2CRR-FMC board located HMC7044

    cat /sys/kernel/debug/iio/iio\:device1/status
    --- PLL1 ---
    Status:    Acquisition
    Using:    CLKIN0 @ 38400000 Hz
    PFD:    7680 kHz
    --- PLL2 ---
    Status:    Locked (Synchronized)
    Frequency:    2949120000 Hz (Autocal cap bank value: 13)
    SYSREF Status:    Valid & Locked
    SYNC Status:    Synchronized
    Lock Status:    Unlocked


    The ADRV9009-ZU11EG RF-SOM located HMC7044
    cat /sys/kernel/debug/iio/iio\:device3/status
    --- PLL1 ---
    Status:    Locked
    Using:    CLKIN1 @ 30720000 Hz
    PFD:    30720 kHz
    --- PLL2 ---
    Status:    Locked (Synchronized)
    Frequency:    2949120000 Hz (Autocal cap bank value: 15)
    SYSREF Status:    Valid & Locked
    SYNC Status:    Synchronized
    Lock Status:    PLL1 & PLL2 Locked

    The clock input buffer ofHMC7044 has been set to 7 (buffer enable, internal 100 ohm termination, AC coupled) which seems to me the right configuration for the attached differential output network, isn't it ?

    Any advice about what could be the cause of the problem ?

    As mentioned AD9545 seems to operate properly, the issue must be located somewhere else (connection between AD9545 and HMC7044 or its configuration).

    Regards, Joel

  • In the end the HMC7044 on the carrier board was able to lock on the reference clock generated using the AD9545 on CLKIN0.

    Regards, Joel