AD4630-24
Recommended for New Designs
The AD4630-24/AD4632-24 are two-channel, simultaneous sampling, Easy Driveâ„¢, 2 MSPS or 500 kSPS successive approximation register (SAR) analog-to-digital...
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AD4630-24 on Analog.com
NathanT - Moved from Precision ADCs to FPGA Reference Designs. Post date updated from Thursday, May 30, 2024 9:16 PM UTC to Monday, June 10, 2024 10:43 AM UTC to reflect the move.
Hi Chaii,
Sorry for the delay, but only now I notice step 3 is wrong.
Step 3 should be:
projects/ad4630_fmc/zed$ export ADI_IGNORE_VERSION_CHECK=1
projects/ad4630_fmc/zed$ make
Then you will find the system_top.xsa in projects/ad4630_fmc/zed/ad4630_fmc_zed.sdk
To build the BOOT.BIN, you first need the u-boot.elf from the u-boot-xlnx repo that you used before.
In u-boot-xlnx folder, do you remember that you ran make distclean -> make zynq_zed_defconfig -> make? I showed you in my screenshot. After that, you need to run cp u-boot "./u-boot_${defcfg//_defconfig/}.elf" to add the .elf extension to the u-boot. Then you use u-boot.elf to generate the BOOT.BIN.
In the folder projects/ad4630_fmc/zed you need to have the u-boot.elf and the system_top.xsa.
Then generate the BOOT.BIN, using this script: https://wiki.analog.com/resources/tools-software/linux-software/build-the-zynq-boot-image
Can you also please confirm what repo I should use to grab samples that are being sent from the zedboard?
After you have the BOOT.BIN, uImage and devicetree.dtb in your BOOT partition of the SD card, and you turn on Zedboard, you can connect to it an UART cable and an Ethernet cable, and through UART to find the IP of the board. Then using that IP, you can use IIO Oscilloscope application.
Just download it from here, open it, and do step 2 from here: https://wiki.analog.com/resources/tools-software/linux-software/iio_oscilloscope#running_remote
Best regards,
Iulia
Hi Iulia,
Thank you for all your help on this! Using your additional steps, I am able to generate the SD Card and the correct build files. I tested using the python example here (https://github.com/analogdevicesinc/pyadi-iio/blob/master/examples/ad4630/ad4630_example_simple_plot.py) with success. I had to modify a line in ad4630.py that was erroring (something to do with if "differential" in ch.name:"). But after doing that, I was able to capture signals using the process to build from scratch.
Best