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Building HDL from Reference Files

Category: Hardware
Product Number: AD4630-24
We're having trouble building the HDL from source and capturing samples using the python scripts from github. We're using the board design available here ( and the python drivers here ( to capture data.

Here our are steps for generating the build image:
We're pulling the repo down, following the steps here( to build the .xsa. Then running this script to generate the BOOT.bin based on these steps ( We're using the boot files that came with the sdcard from zynq-common.

We've tried building in both Vivado/Vitas 2021. and 2023. I can tell the capture is not correct when we are using test signals to capture.

We also verified the zedboard and FMC card are working by using the SD card that came with the board and the same python script to capture data with the SD card that came with the board.
Any thoughts on what could be wrong with our build process? Does anyone have experience using the HDL from GitHub to work with this FMC card?

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