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VCK190 + AD9082 with S=1

Category: Hardware
Product Number: AD9082

Hi,

I'm trying to the build the AD9082-FMCA-EBZ reference design for VCK190, using Cygwin.
I have managed to build the design successfully with the default JESD parameters, 
i.e. using the command "make" with no parameters.

However, I need to build the design with RX_JESD_S = TX_JESD_S = 1.
When doing so, 
using the command "make RX_JESD_S=1 TX_JESD_S=1", 
the build process appears to get stuck - no errors are reported, but the process is never completed (I have waited for hours and days), 
and the text logs files stop to advance.

I have tried both the 'hdl_2022_r2' branch with Vivado 2022.2, and the 'main' branch with Vivado 2023.2.

Is it possible to build the project with these parameters?

Thank you very much,
EW1



grammar
[edited by: EW1 at 6:43 PM (GMT -4) on 14 May 2024]

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