Building an HDL Project

DanA5

on May 13, 2024

Category: Software

Hi,

I am trying to Build an HDL project of one of the reference designs but am failing when invoking make. I am currently following this: Build an HDL project — HDL documentation (analogdevicesinc.github.io). I am using Cygwin

First I'm attaching the screen shot of the actual problem and where I am stuck:

I am using VIVADO version 2019.1. I have it fully installed and I've updated the .bashrc file as follows:

I've basically update the above according to my understanding of what it says to do in "Setup and check your environment". After I do this, I simply exit Cygwin and open the app again. Not sure if I'm doing this process correctly.

Also, the "verify your environment setup" is giving me the following:

As can be seen above, the "which vivado" is failing. I don't know why it's failing, and if that has anything to do with the make failing. Please advise.

Also in "Setup the HDL repository", it says to clone using "git clone git@github.com:analogdevicesinc/hdl.git", however i cloned using "git clone github.com/.../hdl.git.". The latter seems to work without the complications of the key requirement thing. I don't really get it, but I thought I'd mention it in case that could also be a clue to the problem.

Thank you,

Tags: software

Parents

0 travisfcollins

on May 13, 2024 1:57 PM
In your .bashrc, the directories appended to PATH should not include colons as they used as path dividers. So convert the "C:/" -> "C/"

-Travis
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0 DanA5

on May 13, 2024 3:44 PM in reply to travisfcollins

Hi, thanks for the quick response. I changed it to "C/" and the "which vivado" now returns a valid path.

But I still get a fail when I invoke the make. Can you please advise? See below screenshot and also the .log file created. One difference I'm noticing is that before the make would fail almost immediately, and now it seems that it is taking a few seconds (as if it's actually working), but it generates the same end result so I can't explain it:

Fullscreen ad_ip_jesd204_tpl_dac_ip.log Download

****** Vivado v2019.1 (64-bit)
  **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
  **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.

source ad_ip_jesd204_tpl_dac_ip.tcl
# source ../../scripts/adi_env.tcl
## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]]
## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]]
## if [info exists ::env(ADI_HDL_DIR)] {
##   set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)]
## }
## if [info exists ::env(ADI_GHDL_DIR)] {
##   set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)]
## }
# source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl
### variable auto_set_param_list
### variable auto_set_param_list_overwritable
### variable fpga_series_list
### variable fpga_family_list
### variable speed_grade_list
### variable dev_package_list
### variable xcvr_type_list
### variable fpga_voltage_list
### set auto_set_param_list { \
###           DEV_PACKAGE \
###           SPEED_GRADE \
###           FPGA_FAMILY \
###           FPGA_TECHNOLOGY }
### set auto_set_param_list_overwritable { \
###           FPGA_VOLTAGE \
###           XCVR_TYPE }
### set fpga_technology_list { \
###         { Unknown     0 } \
###         { 7series     1 } \
###         { ultrascale  2 } \
###         { ultrascale+ 3 }}
### set fpga_family_list { \
###         { Unknown 0 } \
###         { artix   1 } \
###         { kintex  2 } \
###         { virtex  3 } \
###         { zynq    4 }}
### set speed_grade_list { \
###         { Unknown 0  } \
###         { -1      10 } \
###         { -1L     11 } \
###         { -1H     12 } \
###         { -1HV    13 } \
###         { -1LV    14 } \
###         { -2      20 } \
###         { -2L     21 } \
###         { -2LV    22 } \
###         { -3      30 }}
### set dev_package_list { \
###         { Unknown 0  } \
###         { rf      1  } \
###         { fl      2  } \
###         { ff      3  } \
###         { fb      4  } \
###         { hc      5  } \
###         { fh      6  } \
###         { cs      7  } \
###         { cp      8  } \
###         { ft      9  } \
###         { fg      10 } \
###         { sb      11 } \
###         { rb      12 } \
###         { rs      13 } \
###         { cl      14 } \
###         { sf      15 } \
###         { ba      16 } \
###         { fa      17 }}
### set xcvr_type_list { \
###         { Unknown             0 } \
###         { GTPE2_NOT_SUPPORTED 1 } \
###         { GTXE2               2 } \
###         { GTHE2_NOT_SUPPORTED 3 } \
###         { GTZE2_NOT_SUPPORTED 4 } \
###         { GTHE3               5 } \
###         { GTYE3_NOT_SUPPORTED 6 } \
###         { GTRE4_NOT_SUPPORTED 7 } \
###         { GTHE4               8 } \
###         { GTYE4               9 } \
###         { GTME4_NOT_SUPPORTED 10}}
### set fpga_voltage_list {0 5000} ;
### proc adi_device_spec {cellpath param} {
### 
###   set list_pointer [string tolower $param]
###   set list_pointer [append list_pointer "_list"]
### 
###   upvar 1 $list_pointer $list_pointer
### 
###   set ip [get_bd_cells $cellpath]
###   set part [get_property PART [current_project]]
### 
###   switch -regexp -- $param {
###       FPGA_TECHNOLOGY {
###           switch  -regexp -- $part {
###              ^xc7    {set series_name 7series}
###              ^xczu   {set series_name ultrascale+}
###              ^xc.u.p {set series_name ultrascale+}
###              ^xc.u   {set series_name ultrascale }
###              default {
###                  puts "Undefined fpga technology for \"$part\"!"
###                  exit -1
###              }
###           }
###           return "$series_name"
###       }
###       FPGA_FAMILY {
###           set fpga_family [get_property FAMILY $part]
###           foreach i $fpga_family_list {
###               regexp ^[lindex $i 0] $fpga_family matched
###           }
###           return "$matched"
###       }
###       SPEED_GRADE {
###           set speed_grade [get_property SPEED $part]
###           return "$speed_grade"
###       }
###       DEV_PACKAGE {
###           set dev_package [get_property PACKAGE $part]
###           foreach i $dev_package_list {
###               regexp ^[lindex $i 0] $dev_package matched
###           }
###           return "$matched"
###       }
###       XCVR_TYPE {
###           set matched ""
###           set dev_transcivers "none"
###           foreach x [list_property $part] {
###               regexp ^GT..._TRANSCEIVERS $x dev_transcivers
###           }
###           foreach i $xcvr_type_list {
###               regexp ^[lindex $i 0] $dev_transcivers matched
###           }
###           if { $matched eq "" } {
###                puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!"
###           }
###           return "$matched"
###       }
###       FPGA_VOLTAGE {
###           set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part]
### 	  set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val)
### 
###           return "$fpga_voltage"
###       }
###       default {
###           puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!"
###       }
###   }
### }
## if {![info exists REQUIRED_VIVADO_VERSION]} {
##   set REQUIRED_VIVADO_VERSION "2018.3"
## }
## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
##   set IGNORE_VERSION_CHECK 1
## } elseif {![info exists IGNORE_VERSION_CHECK]} {
##   set IGNORE_VERSION_CHECK 0
## }
## proc adi_ip_ttcl {ip_name ip_constr_files} {
## 
##   set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]
##   set f [ipx::add_file $ip_constr_files $proj_filegroup]
##   set_property -dict [list \
##     type ttcl \
##   ] $f
##   ipx::reorder_files -front $ip_constr_files $proj_filegroup
## }
## proc adi_ip_sim_ttcl {ip_name ip_files} {
## 
##   set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}]
##   set f [ipx::add_file $ip_files $proj_filegroup]
##   set_property -dict [list \
##     type ttcl \
##   ] $f
##   ipx::reorder_files -front $ip_files $proj_filegroup
## }
## proc adi_ip_bd {ip_name ip_bd_files} {
##   set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]]
##   if {$proj_filegroup == {}} {
##     set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]]
##   }
## 
##   foreach file $ip_bd_files {
##     set f [ipx::add_file $file $proj_filegroup]
##     set_property -dict [list \
##       type tclSource \
##     ] $f
##   }
## }
## proc adi_ip_infer_streaming_interfaces {ip_name} {
## 
##   ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
## 
## }
## proc adi_ip_infer_mm_interfaces {ip_name} {
## 
##   ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
## 
## }
## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} {
##   foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] {
##     set_property ENABLEMENT_DEPENDENCY $dependency $port
##     if {$driver_value != {}} {
##       set_property DRIVER_VALUE $driver_value $port
##     }
##   }
## }
## proc adi_set_bus_dependency {bus prefix dependency} {
##   set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]]
##   adi_set_ports_dependency $prefix $dependency 0
## }
## proc adi_add_port_map {bus phys logic} {
##   set map [ipx::add_port_map $phys $bus]
##   set_property "PHYSICAL_NAME" $phys $map
##   set_property "LOGICAL_NAME" $logic $map
## }
## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} {
##   set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
## 
##   set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
##   set_property "BUS_TYPE_VLNV" $bus_type $bus
##   set_property "INTERFACE_MODE" $mode $bus
## 
##   foreach port_map $port_maps {
##     adi_add_port_map $bus {*}$port_map
##   }
## }
## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} {
##   for {set i 0} {$i < $num} {incr i} {
##     set bus_name [format "%s%d" $bus_name_prefix $i]
##     set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
## 
##     set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
##     set_property "BUS_TYPE_VLNV" $bus_type $bus
##     set_property "INTERFACE_MODE" $mode $bus
## 
##     if {$dependency ne ""} {
##       set bus_dependency [string map [list "{i}" $i] $dependency]
##       set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus
##     }
## 
##     foreach port_map $port_maps {
##       lassign $port_map phys logic width
##       set map [ipx::add_port_map $phys $bus]
##       set_property "PHYSICAL_NAME" $phys $map
##       set_property "LOGICAL_NAME" $logic $map
##       set_property "PHYSICAL_RIGHT" [expr $i*$width] $map
##       set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map
##     }
##   }
## }
## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} {
##   set bus_inf_name_clean [string map {":" "_"} $bus_inf_name]
##   set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"]
##   set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]]
##   set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf
##   set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf
##   set_property display_name $clock_inf_name $clock_inf
##   set clock_map [ipx::add_port_map "CLK" $clock_inf]
##   set_property physical_name $clock_signal_name $clock_map
## 
##   set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf]
##   set_property value $bus_inf_name $assoc_busif
## 
##   if { $reset_signal_name != "" } {
##     set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf]
##     set_property value $reset_signal_name $assoc_reset
## 
##     set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"]
##     set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]]
##     set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf
##     set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf
##     set_property display_name $reset_inf_name $reset_inf
##     set_property interface_mode $reset_signal_mode $reset_inf
##     set reset_map [ipx::add_port_map "RST" $reset_inf]
##     set_property physical_name $reset_signal_name $reset_map
## 
##     set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf]
##     if {[string match {*[Nn]} $reset_signal_name] == 1} {
##       set_property value "ACTIVE_LOW" $reset_polarity
##     } else {
##       set_property value "ACTIVE_HIGH" $reset_polarity
##     }
##   }
## }
## proc adi_ip_add_core_dependencies {vlnvs} {
##   foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] {
##     foreach vlnv $vlnvs {
##       ipx::add_subcore $vlnv $file_group
##     }
##   }
## }
## set ip_constr_files ""
## proc adi_ip_create {ip_name} {
## 
##   global ad_hdl_dir
##   global ad_ghdl_dir
##   global ip_constr_files
##   global REQUIRED_VIVADO_VERSION
##   global IGNORE_VERSION_CHECK
## 
##   set VIVADO_VERSION [version -short]
##   if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
##     puts -nonewline "CRITICAL WARNING: vivado version mismatch; "
##     puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
##     puts -nonewline "got $VIVADO_VERSION.\n"
##   }
## 
##   create_project $ip_name . -force
## 
##   ## Load custom message severity definitions
##   source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl
## 
##   set ip_constr_files ""
##   set lib_dirs $ad_hdl_dir/library
##   if {$ad_hdl_dir ne $ad_ghdl_dir} {
##     lappend lib_dirs $ad_ghdl_dir/library
##   }
## 
##   set_property ip_repo_paths $lib_dirs [current_fileset]
##   update_ip_catalog
## }
## proc adi_ip_files {ip_name ip_files} {
## 
##   global ip_constr_files
## 
##   set ip_constr_files ""
##   foreach m_file $ip_files {
##     if {[file extension $m_file] eq ".xdc"} {
##       lappend ip_constr_files $m_file
##       add_files -norecurse -fileset constrs_1 $m_file
##     }
##   }
## 
##   set proj_fileset [get_filesets sources_1]
##   add_files -norecurse -scan_for_includes -fileset $proj_fileset $ip_files
##   set_property "top" "$ip_name" $proj_fileset
## }
## proc adi_ip_properties_lite {ip_name} {
## 
##   global ip_constr_files
## 
##   ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices
##   set_property name $ip_name [ipx::current_core]
##   set_property vendor_display_name {Analog Devices} [ipx::current_core]
##   set_property company_url {http://www.analog.com} [ipx::current_core]
## 
##   set i_families ""
##   foreach i_part [get_parts] {
##     lappend i_families [get_property FAMILY $i_part]
##   }
##   set i_families [lsort -unique $i_families]
##   set s_families [get_property supported_families [ipx::current_core]]
##   foreach i_family $i_families {
##     set s_families "$s_families $i_family Production"
##     set s_families "$s_families $i_family Beta"
##   }
##   set_property supported_families $s_families [ipx::current_core]
##   ipx::save_core
## 
##   ipx::remove_all_bus_interface [ipx::current_core]
##   set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]]
##   foreach map $memory_maps {
##     ipx::remove_memory_map [lindex $map 2] [ipx::current_core ]
##   }
##   ipx::save_core
## 
##   set i_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]
##   foreach i_file $ip_constr_files {
##     set i_module [file tail $i_file]
##     regsub {_constr\.xdc} $i_module {} i_module
##     ipx::add_file $i_file $i_filegroup
##     ipx::reorder_files -front $i_file $i_filegroup
##     set_property SCOPED_TO_REF $i_module [ipx::get_files $i_file -of_objects $i_filegroup]
##   }
##   ipx::save_core
## }
## proc adi_ip_properties {ip_name} {
## 
##   adi_ip_properties_lite $ip_name
## 
##   ipx::infer_bus_interface {\
##     s_axi_awvalid \
##     s_axi_awaddr \
##     s_axi_awprot \
##     s_axi_awready \
##     s_axi_wvalid \
##     s_axi_wdata \
##     s_axi_wstrb \
##     s_axi_wready \
##     s_axi_bvalid \
##     s_axi_bresp \
## 
##     s_axi_bready \
##     s_axi_arvalid \
##     s_axi_araddr \
##     s_axi_arprot \
##     s_axi_arready \
##     s_axi_rvalid \
##     s_axi_rdata \
##     s_axi_rresp \
##     s_axi_rready} \
##   xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
## 
##   ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
##   ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
## 
##   set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1]
##   set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1]
## 
##   if {$raddr_width != $waddr_width} {
##     puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width]
##     set range 65536
##   } else {
##     if {$raddr_width >= 16} {
##       set range 65536
##     } else {
##       set range [expr 1 << $raddr_width]
##     }
##   }
## 
##   ipx::add_memory_map {s_axi} [ipx::current_core]
##   set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
##   ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
##   set_property range $range [ipx::get_address_blocks axi_lite \
##     -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
##   ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core]
##   ipx::save_core
## }
## proc adi_init_bd_tcl {} {
## 
##   global auto_set_param_list
##   global auto_set_param_list_overwritable
##   set cc [ipx::current_core]
## 
##   if { [file exists bd] } {
##     file delete -force bd
##   }
##   file mkdir bd
## 
##   set bd_tcl [open "bd/bd.tcl" w]
## 
##   puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!"
##   puts $bd_tcl "proc init {cellpath otherInfo} {"
##   puts $bd_tcl "  set ip \[get_bd_cells \$cellpath\]"
##   puts $bd_tcl ""
##   set auto_set_param ""
##   foreach i $auto_set_param_list {
##     if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
##       append auto_set_param "    $i \\\n"
##     }
##   }
##   if { $auto_set_param ne "" } {
##     puts $bd_tcl "  bd::mark_propagate_only \$ip \" \\"
##     regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param
##     puts $bd_tcl $auto_set_param
##   }
## 
##   set auto_set_overwritable_param ""
##   foreach i $auto_set_param_list_overwritable {
##     if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
##       append auto_set_overwritable_param "    $i \\\n"
##     }
##   }
##   if { $auto_set_overwritable_param ne "" } {
##     puts $bd_tcl "  bd::mark_propagate_override \$ip \" \\"
##     regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param
##     puts $bd_tcl $auto_set_overwritable_param
##   }
##   puts $bd_tcl "  adi_auto_assign_device_spec \$cellpath"
##   puts $bd_tcl "}"
##   puts $bd_tcl ""
##   puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)"
##   puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {"
##   puts $bd_tcl ""
##   puts $bd_tcl "  set ip \[get_bd_cells \$cellpath\]"
##   puts $bd_tcl "  set ip_param_list \[list_property \$ip\]"
##   puts $bd_tcl "  set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]"
##   puts $bd_tcl ""
##   puts $bd_tcl "  set parent_dir \"../\""
##   puts $bd_tcl "  for {set x 1} {\$x<=4} {incr x} {"
##   puts $bd_tcl "    set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl"
##   puts $bd_tcl "    if { \[file exists \$linkname\] } {"
##   puts $bd_tcl "      source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl"
##   puts $bd_tcl "      break"
##   puts $bd_tcl "    }"
##   puts $bd_tcl "    append parent_dir \"../\""
##   puts $bd_tcl "  }"
##   puts $bd_tcl ""
##   puts $bd_tcl "  # Find predefindes auto assignable parameters"
##   puts $bd_tcl "  foreach i \$auto_set_param_list {"
##   puts $bd_tcl "    if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
##   puts $bd_tcl "      set val \[adi_device_spec \$cellpath \$i\]"
##   puts $bd_tcl "      set_property CONFIG.\$i \$val \$ip"
##   puts $bd_tcl "    }"
##   puts $bd_tcl "  }"
##   puts $bd_tcl ""
##   puts $bd_tcl "  # Find predefindes auto assignable/overwritable parameters"
##   puts $bd_tcl "  foreach i \$auto_set_param_list_overwritable {"
##   puts $bd_tcl "    if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
##   puts $bd_tcl "      set val \[adi_device_spec \$cellpath \$i\]"
##   puts $bd_tcl "      set_property CONFIG.\$i \$val \$ip"
##   puts $bd_tcl "    }"
##   puts $bd_tcl "  }"
##   puts $bd_tcl "}"
##   puts $bd_tcl ""
##   close $bd_tcl
## 
##   set proj_fileset [get_filesets sources_1]
##   add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl"
## 
##   set local_mk [open "temporary_case_dependencies.mk" w]
##   seek $local_mk 0 start
##   puts $local_mk "CLEAN_TARGET += bd"
##   puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk"
##   close $local_mk
## }
## proc adi_add_auto_fpga_spec_params {} {
## 
##   global auto_set_param_list
##   global auto_set_param_list_overwritable
##   set cc [ipx::current_core]
## 
##   foreach i $auto_set_param_list {
##     if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
##       adi_add_device_spec_param $i
##     }
##   }
##   foreach i $auto_set_param_list_overwritable {
##     if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
##       adi_add_device_spec_param $i
##     }
##   }
## }
## proc adi_add_device_spec_param {ip_param} {
## 
##   set cc [ipx::current_core]
## 
##   set list_pointer [string tolower $ip_param]
##   set list_pointer [append list_pointer "_list"]
## 
##   global $list_pointer
## 
##   # set j 1D list from the original list
##   foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]}
## 
##   # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL)
##   if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} {
##     set_property -dict [list \
##       "value_validation_type" "range" \
##       "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \
##       "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \
##     [ipx::get_user_parameters $ip_param -of_objects $cc]
##   } else {
##     set_property -dict [list \
##       "value_validation_type" "pairs" \
##       "value_validation_pairs" $j ] \
##     [ipx::get_user_parameters $ip_param -of_objects $cc]
##   }
## 
##   # FPGA info grup
##   set info_group_name "FPGA info"
##   set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet]
##   if { [string trim $info_group] eq "" } {
##     set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
##     set info_group [ipgui::add_group -name $info_group_name -component $cc \
##         -parent $page0 -display_name $info_group_name]
##   }
## 
##   set p [ipgui::get_guiparamspec -name $ip_param -component $cc]
##   set_property -dict [list "widget" "comboBox" ] $p
##   ipgui::move_param -component $cc -order 0 $p -parent $info_group
## }
## proc adi_if_define {name} {
## 
##   ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0
##   ipx::create_bus_definition analog.com interface $name 1.0
## 
##   set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs]
##   set_property xml_file_name ${name}.xml [ipx::current_busdef]
##   set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs]
## 
##   ipx::save_abstraction_definition [ipx::current_busabs]
##   ipx::save_bus_definition [ipx::current_busdef]
## }
## proc adi_if_ports {dir width name {type none}} {
## 
##   ipx::add_bus_abstraction_port $name [ipx::current_busabs]
##   set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]]
##   set_property master_presence required $m_intf
##   set_property slave_presence  required $m_intf
##   set_property master_width $width $m_intf
##   set_property slave_width  $width $m_intf
## 
##   set m_dir "in"
##   set s_dir "out"
##   if {$dir eq "output"} {
##     set m_dir "out"
##     set s_dir "in"
##   }
## 
##   set_property master_direction $m_dir $m_intf
##   set_property slave_direction  $s_dir $m_intf
## 
##   if {$type ne "none"} {
##     set_property is_${type} true $m_intf
##   }
## 
##   ipx::save_bus_definition [ipx::current_busdef]
##   ipx::save_abstraction_definition [ipx::current_busabs]
## }
## proc adi_if_infer_bus {if_name mode name maps} {
## 
##   ipx::add_bus_interface $name [ipx::current_core]
##   set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]]
##   set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if
##   set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if
##   set_property interface_mode $mode $m_bus_if
## 
##   foreach map $maps  {
##     set m_maps [regexp -all -inline {\S+} $map]
##     lassign $m_maps p_name p_map
##     ipx::add_port_map $p_name $m_bus_if
##     set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if]
##   }
## }
# adi_ip_create ad_ip_jesd204_tpl_dac
CRITICAL WARNING: vivado version mismatch; expected 2018.3, got 2019.1.
## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING
## set_msg_config -id {BD 41-1343} -new_severity WARNING
## set_msg_config -id {BD 41-1306} -new_severity WARNING
## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR
## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO
## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO
## set_msg_config -id {IP_Flow 19-459} -new_severity INFO
## set_msg_config -id {Synth 8-3331} -new_severity INFO
## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO
## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING
## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/cygwin64/home/dan5215/adi/hdl/library'.
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'c:/cygwin64/home/dan5215/adi/ghdl/library'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2019.1/data/ip'.
# adi_ip_files ad_ip_jesd204_tpl_dac [list \
#   "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
#   "$ad_hdl_dir/library/common/ad_dds_sine.v" \
#   "$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \
#   "$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \
#   "$ad_hdl_dir/library/common/ad_dds_2.v" \
#   "$ad_hdl_dir/library/common/ad_dds_1.v" \
#   "$ad_hdl_dir/library/common/ad_dds.v" \
#   "$ad_hdl_dir/library/common/ad_perfect_shuffle.v" \
#   "$ad_hdl_dir/library/common/ad_rst.v" \
#   "$ad_hdl_dir/library/common/up_axi.v" \
#   "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
#   "$ad_hdl_dir/library/common/up_xfer_status.v" \
#   "$ad_hdl_dir/library/common/up_clock_mon.v" \
#   "$ad_hdl_dir/library/common/up_dac_common.v" \
#   "$ad_hdl_dir/library/common/up_dac_channel.v" \
#   "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
#   "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
#   "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
#   "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
#   "../ad_ip_jesd204_tpl_common/up_tpl_common.v" \
#   "ad_ip_jesd204_tpl_dac_channel.v" \
#   "ad_ip_jesd204_tpl_dac_core.v" \
#   "ad_ip_jesd204_tpl_dac_framer.v" \
#   "ad_ip_jesd204_tpl_dac_regmap.v" \
#   "ad_ip_jesd204_tpl_dac_pn.v" \
#   "ad_ip_jesd204_tpl_dac.v" ]
# adi_ip_properties ad_ip_jesd204_tpl_dac
INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/ad_dds.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/ad_dds_1.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/ad_dds_2.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/ad_dds_cordic_pipe.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/ad_dds_sine_cordic.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/ad_perfect_shuffle.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/ad_rst.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/up_axi.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/up_clock_mon.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/up_dac_channel.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/up_dac_common.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/up_xfer_status.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/ad_dds.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/ad_dds_1.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/ad_dds_2.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/ad_dds_cordic_pipe.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/ad_dds_sine_cordic.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/ad_perfect_shuffle.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/ad_rst.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/up_axi.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/up_clock_mon.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/up_dac_channel.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/up_dac_common.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/up_xfer_status.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
WARNING: [IP_Flow 19-5150] The Range '(NUM_CHANNELS - 1):0' is present in all ports of the interface 'dac'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type slave.
WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave.
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
INFO: [IP_Flow 19-5107] Inferred bus interface 'dac' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave.
WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
INFO: [IP_Flow 19-5107] Inferred bus interface 'link' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
WARNING: [IP_Flow 19-5150] The Range '(((NUM_LANES * 8) * OCTETS_PER_BEAT) - 1):0' is present in all ports of the interface 'link'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
WARNING: [IP_Flow 19-5150] The Range '(NUM_CHANNELS - 1):0' is present in all ports of the interface 'interface_spi_engine_offload_ctrl'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'link_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'.
INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'.
WARNING: [IP_Flow 19-1965] Bus Interface 'dac': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
WARNING: [IP_Flow 19-1965] Bus Interface 'dac': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
WARNING: [IP_Flow 19-1965] Bus Interface 'link': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
WARNING: [IP_Flow 19-3153] Bus Interface 'link_clk': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
INFO: [IP_Flow 19-4623] Unrecognized family  azynquplus.  Please verify spelling and reissue command to set the supported files.
INFO: [IP_Flow 19-4623] Unrecognized family  azynquplus.  Please verify spelling and reissue command to set the supported files.
WARNING: [IP_Flow 19-1971] File named "../../../../../../dan5215/adi/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
ERROR: [IP_Flow 19-851] Cannot find !C:/cygwin64/home/dan5215/adi/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc1! to reorder: "(null)".�
ERROR: [Common 17-39] 'ipx::reorder_files' failed due to earlier errors.

    while executing
"ipx::reorder_files -front $i_file $i_filegroup"
    ("foreach" body line 5)
    invoked from within
"foreach i_file $ip_constr_files {
    set i_module [file tail $i_file]
    regsub {_constr\.xdc} $i_module {} i_module
    ipx::add_file $i_file $i_fi..."
    (procedure "adi_ip_properties_lite" line 31)
    invoked from within
"adi_ip_properties_lite $ip_name"
    (procedure "adi_ip_properties" line 3)
    invoked from within
"adi_ip_properties ad_ip_jesd204_tpl_dac"
    (file "ad_ip_jesd204_tpl_dac_ip.tcl" line 56)
INFO: [Common 17-206] Exiting Vivado at Mon May 13 20:32:19 2024...

0 DanA5
on May 16, 2024 2:24 PM in reply to DanA5
Hi, following up on this. Any thoughts?
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0 travisfcollins

on May 16, 2024 3:51 PM in reply to DanA5
If you have the license it doesn't mean the part libraries are installed. I would check "Help > Add Design Tools or Device". Make sure US+ is there.

If that doesn't help I would contact AMD support.

-Travis
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0 DanA5
on May 16, 2024 4:52 PM in reply to travisfcollins
I was actually using VIVADO 2023.1 and that definitely has the US+ installed including the part on the ZCU101, and I've also been programming it so I know it works. For the VIVADO 19.1 you might be right, the part on the ZCU101 may not be installed I realize now. I only selected the 19.1 because you don't seem to have any designs on github for 2023.1, and I have the 19.1 also installed on my machine. Let me figure this out and I'll get back to you here.

Thanks,
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0 DanA5
on May 31, 2024 4:38 PM in reply to DanA5
Hi,

Thanks for your help. So I figured out the previous issue - as you said, the part libraries were not installed so I switched to Vivado 2021.2 where the parts are installed, and the make was successful. But I'm stuck now with the part of generating a new BOOT.BIN.

Here is what I did thus far:

1. I prepared the SD card successfully, per the instructions.

2. I copied the bootgen_sysfiles.tgz from the SD flash from the path in figure 1, to the path in figure 2 (which is the project I build using make). I unzipped twice per the instructions and got all the .elf files (see figure 2)

3. Next I went to Reference, How to build the Zynq boot image BOOT.BIN:

https://wiki.analog.com/resources/tools-software/linux-software/build-the-zynq-boot-image

and I downloaded build_boot_bin.sh. I then made it executable. All per the instructions there.

I'm stuck in the "Usage" part. I basically type the command:

build_boot_bin.sh system_top.xsa u-boot.elf [output-archive]

But I get "build_boot_bin.sh: command not found" (see figure 3).
Can you please shed some light into what I may be doing wrong? Thanks

Figure 1

Figure 2

Figure 3
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0 iulia

on Jun 3, 2024 6:56 AM in reply to DanA5
Removed the comment as it doesn't apply for this case, because the wrong link was used.
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0 DanA5
on Jun 3, 2024 3:52 PM in reply to iulia
Hi,

Thanks for clarifying that. So I've made some progress but I now get an error when running the build_boot_bin.sh script that Xvfb is not available on the system (see figure 1 below). I've searched for this utility/package in the Cygwin installation to add it but it does not exist when I serach for it (see figure 2)

Figure 1:

Figure 2:
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0 iulia

on Jun 4, 2024 3:22 AM in reply to DanA5
https://cygwin.com/packages/summary/xorg-server-extra.html

This I found after a simple search on Google "install xvfb on cygwin" and it was the first result.

Please search the internet a little bit more before you ask us, as this is not connected to ADI in any way, this is regarding your system.
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0 iulia

on Jun 4, 2024 3:58 AM in reply to iulia
I apologize, only now I noticed that you're using the wrong script. You took the one for Zynq FPGAs and not ZynqMP (ZCU102). My previous comment with the link to the xvfb package is still valid, you still have to install that.

This is the correct link from where to take the script: https://wiki.analog.com/resources/tools-software/linux-software/build-the-zynqmp-boot-image

Best regards,
Iulia
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0 DanA5
on Jun 4, 2024 12:13 PM in reply to iulia
Thank you very much for all your help, but please do not assume I do not do anything before I ask you. I have been working on this stuff for months now, and still have gotten not very far. What might be very obvious to you is sometimes not obvious to someone that is not familiar with this entire system and tools, and by the way that is only "my system" because you essentially require me to use this system or I can't do anything. I'm an FPGA design engineer. I specialize in DSP and DACS and ADCs, but just to get the ADI reference design to work on this carrier board requires a whole lot of tools I am not familiar with - Linux/Cygwin, git, etc, as well as tcl scripts (you'll be surprised but most FPGA designers use the GUI interface and do not heavily use TCL scripts). Your wiki tutorials and references are not 100% perfect, and they constantly branch out to almost infinity and I can't even keep track of all the wiki tabs I have open. This is not a rant, but just a request to please be more patient with me. I am learning this stuff as I am going through your wiki tutorials and references, and hopefully your help.

I have actually found this xorg-server link as well but did not connect that this what I need to install, and not just xvfb. Again, because I'm new to Cygwin (and Linux!).

Thanks
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0 DanA5
on Jun 4, 2024 5:27 PM in reply to iulia
Thank you, I downloaded the correct script now. After stumbling through a couple more problems that I managed to somehow resolve, I'm now stuck at the following Error/s. I get some "couldn't figure out compiler's library directory" (please see figure 2).

First, just to make sure I did it right, I wrote out the following command (figure 1). I used the b131.elf option, according to the wiki. Not sure if that's correct though.

And here is the rest of the output including the errors (figure 2): It's hard for me to understand the output. For example, why is it opening

/cygdrive/C/Xilinx/Vitis/2021.2/gnu/microblaze/nt

when I'm not using microblaze.. I don't really get it. But you can see the actual error below.

Thanks,
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0 DanA5
on Jun 4, 2024 5:27 PM in reply to iulia
Thank you, I downloaded the correct script now. After stumbling through a couple more problems that I managed to somehow resolve, I'm now stuck at the following Error/s. I get some "couldn't figure out compiler's library directory" (please see figure 2).

First, just to make sure I did it right, I wrote out the following command (figure 1). I used the b131.elf option, according to the wiki. Not sure if that's correct though.

And here is the rest of the output including the errors (figure 2): It's hard for me to understand the output. For example, why is it opening

/cygdrive/C/Xilinx/Vitis/2021.2/gnu/microblaze/nt

when I'm not using microblaze.. I don't really get it. But you can see the actual error below.

Thanks,
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0 iulia

on Jun 5, 2024 3:28 AM in reply to DanA5
Please attach the output of the commands vitis -v and vitis --version

I need to check something regarding this output.

Best regards,
Iulia
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0 iulia

on Jun 5, 2024 7:03 AM in reply to iulia
Additionally, can you run again the script build_zynqmp_boot_bin.sh? Because I did some updates on it and it might solve your issue, although I wasn’t able to replicate it on my system.
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0 DanA5
on Jun 5, 2024 10:29 AM in reply to iulia
See below
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0 DanA5
on Jun 5, 2024 10:38 AM in reply to iulia
I ran it again and same thing. Not sure what you mean by you did updates. Just to make sure, here is what I did; I downloaded the script again, made it executable, and then ran it again like I posted in the other post.

thanks,
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0 iulia

on Jun 6, 2024 8:57 AM in reply to DanA5
Sorry for the delay, but we had some technical issues with the site and I couldn't reply.

Thanks for the screenshot.

I updated the way the Vitis version is extracted from the above commands, as I noticed that on Cygwin it is printed differently now.

So if you can download again this script: https://github.com/analogdevicesinc/wiki-scripts/blob/main/zynqmp_boot_bin/build_zynqmp_boot_bin.sh (updated), make it executable and run it again, but this time to try the other method, with "download" as parameter, and not "bl31.elf":
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0 DanA5
on Jun 6, 2024 4:54 PM in reply to iulia
Hi, thank you. There's definitely some progress, but I'm still having problems.

I downloaded the updated script, made it executable, and ran it (see figure 1), but the compilation is now aborted with a fatal error (see figure 2) and that is preceded with a bunch of syntax errors and it's pointing to directories/files I can't even locate

figure 1:

Figure 2:
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0 DanA5
on Jun 10, 2024 9:46 AM in reply to DanA5
Hi,

Following up on this. Any thoughts?
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0 DanA5
on Jun 11, 2024 5:50 PM in reply to DanA5
Hi again, Following up on this again.

Thanks,
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+1 iulia

on Jun 12, 2024 7:19 AM in reply to DanA5
Hi,

After a lot of debugging with another team as well, we discovered that there's an issue with the type of shell that is set during the process and mainly with the necessary permissions to create some folders & files, all required by the Xilinx tools. This issue is happening only in Cygwin, as it doesn't have all the capabilities of a Linux system which are required by the (Linux) commands that the Xilinx scripts are running.

At this point, it's out of our reach and we have come to the conclusion that we cannot support it anymore in Cygwin. The other options are to check the way Xilinx does it from Vivado GUI (which I am not familiar with), WSL, a Linux virtual machine or nativ Linux to run this script.

Sorry for the inconvenience,
Iulia
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