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Building an HDL Project

Category: Software

Hi,

I am trying to Build an HDL project of one of the reference designs but am failing when invoking make.  I am currently following this: Build an HDL project — HDL documentation (analogdevicesinc.github.io).  I am using Cygwin

First I'm attaching the screen shot of the actual problem and where I am stuck:  

I am using VIVADO version 2019.1.  I have it fully installed and I've updated the .bashrc file as follows:

I've basically update the above according to my understanding of what it says to do in "Setup and check your environment".  After I do this, I simply exit Cygwin and open the app again.  Not sure if I'm doing this process correctly.

Also, the "verify your environment setup" is giving me the following:

As can be seen above, the "which vivado" is failing.  I don't know why it's failing, and if that has anything to do with the make failing.  Please advise.

Also in "Setup the HDL repository", it says to clone using "git clone git@github.com:analogdevicesinc/hdl.git", however i cloned using "git clone github.com/.../hdl.git.".  The latter seems to work without the complications of the key requirement thing.  I don't really get it, but I thought I'd mention it in case that could also be a clue to the problem.

Thank you,

  • In your .bashrc, the directories appended to PATH should not include colons as they used as path dividers. So convert the "C:/" -> "C/"

    -Travis

  • Hi, thanks for the quick response.  I changed it to "C/" and the "which vivado" now returns a valid path.

    But I still get a fail when I invoke the make. Can you please advise?  See below screenshot and also the .log file created.  One difference I'm noticing is that before the make would fail almost immediately, and now it seems that it is taking a few seconds (as if it's actually working), but it generates the same end result so I can't explain it:

    ****** Vivado v2019.1 (64-bit)
      **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
      **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
        ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
    
    source ad_ip_jesd204_tpl_dac_ip.tcl
    # source ../../scripts/adi_env.tcl
    ## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]]
    ## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]]
    ## if [info exists ::env(ADI_HDL_DIR)] {
    ##   set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)]
    ## }
    ## if [info exists ::env(ADI_GHDL_DIR)] {
    ##   set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)]
    ## }
    # source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl
    ## source $ad_hdl_dir/library/scripts/adi_xilinx_device_info_enc.tcl
    ### variable auto_set_param_list
    ### variable auto_set_param_list_overwritable
    ### variable fpga_series_list
    ### variable fpga_family_list
    ### variable speed_grade_list
    ### variable dev_package_list
    ### variable xcvr_type_list
    ### variable fpga_voltage_list
    ### set auto_set_param_list { \
    ###           DEV_PACKAGE \
    ###           SPEED_GRADE \
    ###           FPGA_FAMILY \
    ###           FPGA_TECHNOLOGY }
    ### set auto_set_param_list_overwritable { \
    ###           FPGA_VOLTAGE \
    ###           XCVR_TYPE }
    ### set fpga_technology_list { \
    ###         { Unknown     0 } \
    ###         { 7series     1 } \
    ###         { ultrascale  2 } \
    ###         { ultrascale+ 3 }}
    ### set fpga_family_list { \
    ###         { Unknown 0 } \
    ###         { artix   1 } \
    ###         { kintex  2 } \
    ###         { virtex  3 } \
    ###         { zynq    4 }}
    ### set speed_grade_list { \
    ###         { Unknown 0  } \
    ###         { -1      10 } \
    ###         { -1L     11 } \
    ###         { -1H     12 } \
    ###         { -1HV    13 } \
    ###         { -1LV    14 } \
    ###         { -2      20 } \
    ###         { -2L     21 } \
    ###         { -2LV    22 } \
    ###         { -3      30 }}
    ### set dev_package_list { \
    ###         { Unknown 0  } \
    ###         { rf      1  } \
    ###         { fl      2  } \
    ###         { ff      3  } \
    ###         { fb      4  } \
    ###         { hc      5  } \
    ###         { fh      6  } \
    ###         { cs      7  } \
    ###         { cp      8  } \
    ###         { ft      9  } \
    ###         { fg      10 } \
    ###         { sb      11 } \
    ###         { rb      12 } \
    ###         { rs      13 } \
    ###         { cl      14 } \
    ###         { sf      15 } \
    ###         { ba      16 } \
    ###         { fa      17 }}
    ### set xcvr_type_list { \
    ###         { Unknown             0 } \
    ###         { GTPE2_NOT_SUPPORTED 1 } \
    ###         { GTXE2               2 } \
    ###         { GTHE2_NOT_SUPPORTED 3 } \
    ###         { GTZE2_NOT_SUPPORTED 4 } \
    ###         { GTHE3               5 } \
    ###         { GTYE3_NOT_SUPPORTED 6 } \
    ###         { GTRE4_NOT_SUPPORTED 7 } \
    ###         { GTHE4               8 } \
    ###         { GTYE4               9 } \
    ###         { GTME4_NOT_SUPPORTED 10}}
    ### set fpga_voltage_list {0 5000} ;
    ### proc adi_device_spec {cellpath param} {
    ### 
    ###   set list_pointer [string tolower $param]
    ###   set list_pointer [append list_pointer "_list"]
    ### 
    ###   upvar 1 $list_pointer $list_pointer
    ### 
    ###   set ip [get_bd_cells $cellpath]
    ###   set part [get_property PART [current_project]]
    ### 
    ###   switch -regexp -- $param {
    ###       FPGA_TECHNOLOGY {
    ###           switch  -regexp -- $part {
    ###              ^xc7    {set series_name 7series}
    ###              ^xczu   {set series_name ultrascale+}
    ###              ^xc.u.p {set series_name ultrascale+}
    ###              ^xc.u   {set series_name ultrascale }
    ###              default {
    ###                  puts "Undefined fpga technology for \"$part\"!"
    ###                  exit -1
    ###              }
    ###           }
    ###           return "$series_name"
    ###       }
    ###       FPGA_FAMILY {
    ###           set fpga_family [get_property FAMILY $part]
    ###           foreach i $fpga_family_list {
    ###               regexp ^[lindex $i 0] $fpga_family matched
    ###           }
    ###           return "$matched"
    ###       }
    ###       SPEED_GRADE {
    ###           set speed_grade [get_property SPEED $part]
    ###           return "$speed_grade"
    ###       }
    ###       DEV_PACKAGE {
    ###           set dev_package [get_property PACKAGE $part]
    ###           foreach i $dev_package_list {
    ###               regexp ^[lindex $i 0] $dev_package matched
    ###           }
    ###           return "$matched"
    ###       }
    ###       XCVR_TYPE {
    ###           set matched ""
    ###           set dev_transcivers "none"
    ###           foreach x [list_property $part] {
    ###               regexp ^GT..._TRANSCEIVERS $x dev_transcivers
    ###           }
    ###           foreach i $xcvr_type_list {
    ###               regexp ^[lindex $i 0] $dev_transcivers matched
    ###           }
    ###           if { $matched eq "" } {
    ###                puts "CRITICAL WARNING: \"$dev_transcivers\" TYPE IS NOT SUPPORTED BY ADI!"
    ###           }
    ###           return "$matched"
    ###       }
    ###       FPGA_VOLTAGE {
    ###           set fpga_voltage [get_property REF_OPERATING_VOLTAGE $part]
    ### 	  set fpga_voltage [expr int([expr $fpga_voltage * 1000])] ;# // V to mV conversion(integer val)
    ### 
    ###           return "$fpga_voltage"
    ###       }
    ###       default {
    ###           puts "WARNING: UNDEFINED PARAMETER \"$param\" (adi_device_spec)!"
    ###       }
    ###   }
    ### }
    ## if {![info exists REQUIRED_VIVADO_VERSION]} {
    ##   set REQUIRED_VIVADO_VERSION "2018.3"
    ## }
    ## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
    ##   set IGNORE_VERSION_CHECK 1
    ## } elseif {![info exists IGNORE_VERSION_CHECK]} {
    ##   set IGNORE_VERSION_CHECK 0
    ## }
    ## proc adi_ip_ttcl {ip_name ip_constr_files} {
    ## 
    ##   set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]
    ##   set f [ipx::add_file $ip_constr_files $proj_filegroup]
    ##   set_property -dict [list \
    ##     type ttcl \
    ##   ] $f
    ##   ipx::reorder_files -front $ip_constr_files $proj_filegroup
    ## }
    ## proc adi_ip_sim_ttcl {ip_name ip_files} {
    ## 
    ##   set proj_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *simulation*}]
    ##   set f [ipx::add_file $ip_files $proj_filegroup]
    ##   set_property -dict [list \
    ##     type ttcl \
    ##   ] $f
    ##   ipx::reorder_files -front $ip_files $proj_filegroup
    ## }
    ## proc adi_ip_bd {ip_name ip_bd_files} {
    ##   set proj_filegroup [ipx::get_file_groups xilinx_blockdiagram -of_objects [ipx::current_core]]
    ##   if {$proj_filegroup == {}} {
    ##     set proj_filegroup [ipx::add_file_group -type xilinx_blockdiagram "" [ipx::current_core]]
    ##   }
    ## 
    ##   foreach file $ip_bd_files {
    ##     set f [ipx::add_file $file $proj_filegroup]
    ##     set_property -dict [list \
    ##       type tclSource \
    ##     ] $f
    ##   }
    ## }
    ## proc adi_ip_infer_streaming_interfaces {ip_name} {
    ## 
    ##   ipx::infer_bus_interfaces xilinx.com:interface:axis_rtl:1.0 [ipx::current_core]
    ## 
    ## }
    ## proc adi_ip_infer_mm_interfaces {ip_name} {
    ## 
    ##   ipx::infer_bus_interfaces xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
    ## 
    ## }
    ## proc adi_set_ports_dependency {port_prefix dependency {driver_value {}}} {
    ##   foreach port [ipx::get_ports [format "%s%s" $port_prefix "*"]] {
    ##     set_property ENABLEMENT_DEPENDENCY $dependency $port
    ##     if {$driver_value != {}} {
    ##       set_property DRIVER_VALUE $driver_value $port
    ##     }
    ##   }
    ## }
    ## proc adi_set_bus_dependency {bus prefix dependency} {
    ##   set_property ENABLEMENT_DEPENDENCY $dependency [ipx::get_bus_interfaces $bus -of_objects [ipx::current_core]]
    ##   adi_set_ports_dependency $prefix $dependency 0
    ## }
    ## proc adi_add_port_map {bus phys logic} {
    ##   set map [ipx::add_port_map $phys $bus]
    ##   set_property "PHYSICAL_NAME" $phys $map
    ##   set_property "LOGICAL_NAME" $logic $map
    ## }
    ## proc adi_add_bus {bus_name mode abs_type bus_type port_maps} {
    ##   set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
    ## 
    ##   set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
    ##   set_property "BUS_TYPE_VLNV" $bus_type $bus
    ##   set_property "INTERFACE_MODE" $mode $bus
    ## 
    ##   foreach port_map $port_maps {
    ##     adi_add_port_map $bus {*}$port_map
    ##   }
    ## }
    ## proc adi_add_multi_bus {num bus_name_prefix mode abs_type bus_type port_maps dependency} {
    ##   for {set i 0} {$i < $num} {incr i} {
    ##     set bus_name [format "%s%d" $bus_name_prefix $i]
    ##     set bus [ipx::add_bus_interface $bus_name [ipx::current_core]]
    ## 
    ##     set_property "ABSTRACTION_TYPE_VLNV" $abs_type $bus
    ##     set_property "BUS_TYPE_VLNV" $bus_type $bus
    ##     set_property "INTERFACE_MODE" $mode $bus
    ## 
    ##     if {$dependency ne ""} {
    ##       set bus_dependency [string map [list "{i}" $i] $dependency]
    ##       set_property ENABLEMENT_DEPENDENCY $bus_dependency $bus
    ##     }
    ## 
    ##     foreach port_map $port_maps {
    ##       lassign $port_map phys logic width
    ##       set map [ipx::add_port_map $phys $bus]
    ##       set_property "PHYSICAL_NAME" $phys $map
    ##       set_property "LOGICAL_NAME" $logic $map
    ##       set_property "PHYSICAL_RIGHT" [expr $i*$width] $map
    ##       set_property "PHYSICAL_LEFT" [expr ($i+1)*$width-1] $map
    ##     }
    ##   }
    ## }
    ## proc adi_add_bus_clock {clock_signal_name bus_inf_name {reset_signal_name ""} {reset_signal_mode "slave"}} {
    ##   set bus_inf_name_clean [string map {":" "_"} $bus_inf_name]
    ##   set clock_inf_name [format "%s%s" $bus_inf_name_clean "_signal_clock"]
    ##   set clock_inf [ipx::add_bus_interface $clock_inf_name [ipx::current_core]]
    ##   set_property abstraction_type_vlnv "xilinx.com:signal:clock_rtl:1.0" $clock_inf
    ##   set_property bus_type_vlnv "xilinx.com:signal:clock:1.0" $clock_inf
    ##   set_property display_name $clock_inf_name $clock_inf
    ##   set clock_map [ipx::add_port_map "CLK" $clock_inf]
    ##   set_property physical_name $clock_signal_name $clock_map
    ## 
    ##   set assoc_busif [ipx::add_bus_parameter "ASSOCIATED_BUSIF" $clock_inf]
    ##   set_property value $bus_inf_name $assoc_busif
    ## 
    ##   if { $reset_signal_name != "" } {
    ##     set assoc_reset [ipx::add_bus_parameter "ASSOCIATED_RESET" $clock_inf]
    ##     set_property value $reset_signal_name $assoc_reset
    ## 
    ##     set reset_inf_name [format "%s%s" $bus_inf_name_clean "_signal_reset"]
    ##     set reset_inf [ipx::add_bus_interface $reset_inf_name [ipx::current_core]]
    ##     set_property abstraction_type_vlnv "xilinx.com:signal:reset_rtl:1.0" $reset_inf
    ##     set_property bus_type_vlnv "xilinx.com:signal:reset:1.0" $reset_inf
    ##     set_property display_name $reset_inf_name $reset_inf
    ##     set_property interface_mode $reset_signal_mode $reset_inf
    ##     set reset_map [ipx::add_port_map "RST" $reset_inf]
    ##     set_property physical_name $reset_signal_name $reset_map
    ## 
    ##     set reset_polarity [ipx::add_bus_parameter "POLARITY" $reset_inf]
    ##     if {[string match {*[Nn]} $reset_signal_name] == 1} {
    ##       set_property value "ACTIVE_LOW" $reset_polarity
    ##     } else {
    ##       set_property value "ACTIVE_HIGH" $reset_polarity
    ##     }
    ##   }
    ## }
    ## proc adi_ip_add_core_dependencies {vlnvs} {
    ##   foreach file_group [ipx::get_file_groups * -of_objects [ipx::current_core]] {
    ##     foreach vlnv $vlnvs {
    ##       ipx::add_subcore $vlnv $file_group
    ##     }
    ##   }
    ## }
    ## set ip_constr_files ""
    ## proc adi_ip_create {ip_name} {
    ## 
    ##   global ad_hdl_dir
    ##   global ad_ghdl_dir
    ##   global ip_constr_files
    ##   global REQUIRED_VIVADO_VERSION
    ##   global IGNORE_VERSION_CHECK
    ## 
    ##   set VIVADO_VERSION [version -short]
    ##   if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
    ##     puts -nonewline "CRITICAL WARNING: vivado version mismatch; "
    ##     puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
    ##     puts -nonewline "got $VIVADO_VERSION.\n"
    ##   }
    ## 
    ##   create_project $ip_name . -force
    ## 
    ##   ## Load custom message severity definitions
    ##   source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl
    ## 
    ##   set ip_constr_files ""
    ##   set lib_dirs $ad_hdl_dir/library
    ##   if {$ad_hdl_dir ne $ad_ghdl_dir} {
    ##     lappend lib_dirs $ad_ghdl_dir/library
    ##   }
    ## 
    ##   set_property ip_repo_paths $lib_dirs [current_fileset]
    ##   update_ip_catalog
    ## }
    ## proc adi_ip_files {ip_name ip_files} {
    ## 
    ##   global ip_constr_files
    ## 
    ##   set ip_constr_files ""
    ##   foreach m_file $ip_files {
    ##     if {[file extension $m_file] eq ".xdc"} {
    ##       lappend ip_constr_files $m_file
    ##       add_files -norecurse -fileset constrs_1 $m_file
    ##     }
    ##   }
    ## 
    ##   set proj_fileset [get_filesets sources_1]
    ##   add_files -norecurse -scan_for_includes -fileset $proj_fileset $ip_files
    ##   set_property "top" "$ip_name" $proj_fileset
    ## }
    ## proc adi_ip_properties_lite {ip_name} {
    ## 
    ##   global ip_constr_files
    ## 
    ##   ipx::package_project -root_dir . -vendor analog.com -library user -taxonomy /Analog_Devices
    ##   set_property name $ip_name [ipx::current_core]
    ##   set_property vendor_display_name {Analog Devices} [ipx::current_core]
    ##   set_property company_url {http://www.analog.com} [ipx::current_core]
    ## 
    ##   set i_families ""
    ##   foreach i_part [get_parts] {
    ##     lappend i_families [get_property FAMILY $i_part]
    ##   }
    ##   set i_families [lsort -unique $i_families]
    ##   set s_families [get_property supported_families [ipx::current_core]]
    ##   foreach i_family $i_families {
    ##     set s_families "$s_families $i_family Production"
    ##     set s_families "$s_families $i_family Beta"
    ##   }
    ##   set_property supported_families $s_families [ipx::current_core]
    ##   ipx::save_core
    ## 
    ##   ipx::remove_all_bus_interface [ipx::current_core]
    ##   set memory_maps [ipx::get_memory_maps * -of_objects [ipx::current_core]]
    ##   foreach map $memory_maps {
    ##     ipx::remove_memory_map [lindex $map 2] [ipx::current_core ]
    ##   }
    ##   ipx::save_core
    ## 
    ##   set i_filegroup [ipx::get_file_groups -of_objects [ipx::current_core] -filter {NAME =~ *synthesis*}]
    ##   foreach i_file $ip_constr_files {
    ##     set i_module [file tail $i_file]
    ##     regsub {_constr\.xdc} $i_module {} i_module
    ##     ipx::add_file $i_file $i_filegroup
    ##     ipx::reorder_files -front $i_file $i_filegroup
    ##     set_property SCOPED_TO_REF $i_module [ipx::get_files $i_file -of_objects $i_filegroup]
    ##   }
    ##   ipx::save_core
    ## }
    ## proc adi_ip_properties {ip_name} {
    ## 
    ##   adi_ip_properties_lite $ip_name
    ## 
    ##   ipx::infer_bus_interface {\
    ##     s_axi_awvalid \
    ##     s_axi_awaddr \
    ##     s_axi_awprot \
    ##     s_axi_awready \
    ##     s_axi_wvalid \
    ##     s_axi_wdata \
    ##     s_axi_wstrb \
    ##     s_axi_wready \
    ##     s_axi_bvalid \
    ##     s_axi_bresp \
    ## 
    ##     s_axi_bready \
    ##     s_axi_arvalid \
    ##     s_axi_araddr \
    ##     s_axi_arprot \
    ##     s_axi_arready \
    ##     s_axi_rvalid \
    ##     s_axi_rdata \
    ##     s_axi_rresp \
    ##     s_axi_rready} \
    ##   xilinx.com:interface:aximm_rtl:1.0 [ipx::current_core]
    ## 
    ##   ipx::infer_bus_interface s_axi_aclk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
    ##   ipx::infer_bus_interface s_axi_aresetn xilinx.com:signal:reset_rtl:1.0 [ipx::current_core]
    ## 
    ##   set raddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_araddr -of_objects [ipx::current_core]]] + 1]
    ##   set waddr_width [expr [get_property SIZE_LEFT [ipx::get_ports -nocase true s_axi_awaddr -of_objects [ipx::current_core]]] + 1]
    ## 
    ##   if {$raddr_width != $waddr_width} {
    ##     puts [format "WARNING: AXI address width mismatch for %s (r=%d, w=%d)" $ip_name $raddr_width, $waddr_width]
    ##     set range 65536
    ##   } else {
    ##     if {$raddr_width >= 16} {
    ##       set range 65536
    ##     } else {
    ##       set range [expr 1 << $raddr_width]
    ##     }
    ##   }
    ## 
    ##   ipx::add_memory_map {s_axi} [ipx::current_core]
    ##   set_property slave_memory_map_ref {s_axi} [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
    ##   ipx::add_address_block {axi_lite} [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]
    ##   set_property range $range [ipx::get_address_blocks axi_lite \
    ##     -of_objects [ipx::get_memory_maps s_axi -of_objects [ipx::current_core]]]
    ##   ipx::associate_bus_interfaces -clock s_axi_aclk -reset s_axi_aresetn [ipx::current_core]
    ##   ipx::save_core
    ## }
    ## proc adi_init_bd_tcl {} {
    ## 
    ##   global auto_set_param_list
    ##   global auto_set_param_list_overwritable
    ##   set cc [ipx::current_core]
    ## 
    ##   if { [file exists bd] } {
    ##     file delete -force bd
    ##   }
    ##   file mkdir bd
    ## 
    ##   set bd_tcl [open "bd/bd.tcl" w]
    ## 
    ##   puts $bd_tcl "# SCRIPT AUTO-GENERATED AT BUILD, DO NOT MODIFY!"
    ##   puts $bd_tcl "proc init {cellpath otherInfo} {"
    ##   puts $bd_tcl "  set ip \[get_bd_cells \$cellpath\]"
    ##   puts $bd_tcl ""
    ##   set auto_set_param ""
    ##   foreach i $auto_set_param_list {
    ##     if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
    ##       append auto_set_param "    $i \\\n"
    ##     }
    ##   }
    ##   if { $auto_set_param ne "" } {
    ##     puts $bd_tcl "  bd::mark_propagate_only \$ip \" \\"
    ##     regsub "${i} \\\\" $auto_set_param "$i\"" auto_set_param
    ##     puts $bd_tcl $auto_set_param
    ##   }
    ## 
    ##   set auto_set_overwritable_param ""
    ##   foreach i $auto_set_param_list_overwritable {
    ##     if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne "" } {
    ##       append auto_set_overwritable_param "    $i \\\n"
    ##     }
    ##   }
    ##   if { $auto_set_overwritable_param ne "" } {
    ##     puts $bd_tcl "  bd::mark_propagate_override \$ip \" \\"
    ##     regsub "${i} \\\\" $auto_set_overwritable_param "$i\"" auto_set_overwritable_param
    ##     puts $bd_tcl $auto_set_overwritable_param
    ##   }
    ##   puts $bd_tcl "  adi_auto_assign_device_spec \$cellpath"
    ##   puts $bd_tcl "}"
    ##   puts $bd_tcl ""
    ##   puts $bd_tcl "# auto set parameters defined in auto_set_param_list (adi_xilinx_device_info_enc.tcl)"
    ##   puts $bd_tcl "proc adi_auto_assign_device_spec {cellpath} {"
    ##   puts $bd_tcl ""
    ##   puts $bd_tcl "  set ip \[get_bd_cells \$cellpath\]"
    ##   puts $bd_tcl "  set ip_param_list \[list_property \$ip\]"
    ##   puts $bd_tcl "  set ip_path \[bd::get_vlnv_dir \[get_property VLNV \$ip\]\]"
    ##   puts $bd_tcl ""
    ##   puts $bd_tcl "  set parent_dir \"../\""
    ##   puts $bd_tcl "  for {set x 1} {\$x<=4} {incr x} {"
    ##   puts $bd_tcl "    set linkname \${ip_path}\${parent_dir}scripts/adi_xilinx_device_info_enc.tcl"
    ##   puts $bd_tcl "    if { \[file exists \$linkname\] } {"
    ##   puts $bd_tcl "      source \${ip_path}\${parent_dir}/scripts/adi_xilinx_device_info_enc.tcl"
    ##   puts $bd_tcl "      break"
    ##   puts $bd_tcl "    }"
    ##   puts $bd_tcl "    append parent_dir \"../\""
    ##   puts $bd_tcl "  }"
    ##   puts $bd_tcl ""
    ##   puts $bd_tcl "  # Find predefindes auto assignable parameters"
    ##   puts $bd_tcl "  foreach i \$auto_set_param_list {"
    ##   puts $bd_tcl "    if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
    ##   puts $bd_tcl "      set val \[adi_device_spec \$cellpath \$i\]"
    ##   puts $bd_tcl "      set_property CONFIG.\$i \$val \$ip"
    ##   puts $bd_tcl "    }"
    ##   puts $bd_tcl "  }"
    ##   puts $bd_tcl ""
    ##   puts $bd_tcl "  # Find predefindes auto assignable/overwritable parameters"
    ##   puts $bd_tcl "  foreach i \$auto_set_param_list_overwritable {"
    ##   puts $bd_tcl "    if { \[lsearch \$ip_param_list \"CONFIG.\$i\"\] > 0 } {"
    ##   puts $bd_tcl "      set val \[adi_device_spec \$cellpath \$i\]"
    ##   puts $bd_tcl "      set_property CONFIG.\$i \$val \$ip"
    ##   puts $bd_tcl "    }"
    ##   puts $bd_tcl "  }"
    ##   puts $bd_tcl "}"
    ##   puts $bd_tcl ""
    ##   close $bd_tcl
    ## 
    ##   set proj_fileset [get_filesets sources_1]
    ##   add_files -norecurse -scan_for_includes -fileset $proj_fileset "bd/bd.tcl"
    ## 
    ##   set local_mk [open "temporary_case_dependencies.mk" w]
    ##   seek $local_mk 0 start
    ##   puts $local_mk "CLEAN_TARGET += bd"
    ##   puts $local_mk "CLEAN_TARGET += temporary_case_dependencies.mk"
    ##   close $local_mk
    ## }
    ## proc adi_add_auto_fpga_spec_params {} {
    ## 
    ##   global auto_set_param_list
    ##   global auto_set_param_list_overwritable
    ##   set cc [ipx::current_core]
    ## 
    ##   foreach i $auto_set_param_list {
    ##     if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
    ##       adi_add_device_spec_param $i
    ##     }
    ##   }
    ##   foreach i $auto_set_param_list_overwritable {
    ##     if { [ipx::get_user_parameters $i -of_objects $cc -quiet] ne ""} {
    ##       adi_add_device_spec_param $i
    ##     }
    ##   }
    ## }
    ## proc adi_add_device_spec_param {ip_param} {
    ## 
    ##   set cc [ipx::current_core]
    ## 
    ##   set list_pointer [string tolower $ip_param]
    ##   set list_pointer [append list_pointer "_list"]
    ## 
    ##   global $list_pointer
    ## 
    ##   # set j 1D list from the original list
    ##   foreach i [subst $$list_pointer] {lappend j [lindex $i 0] [lindex $i 1]}
    ## 
    ##   # set ranges or validation pairs (show x in GUI assign the corresponding y to HDL)
    ##   if { [llength [subst $$list_pointer]] == 2 && [llength $j] == 4} {
    ##     set_property -dict [list \
    ##       "value_validation_type" "range" \
    ##       "value_validation_range_minimum" [lindex [subst $$list_pointer] 0] \
    ##       "value_validation_range_maximum" [lindex [subst $$list_pointer] 1] ] \
    ##     [ipx::get_user_parameters $ip_param -of_objects $cc]
    ##   } else {
    ##     set_property -dict [list \
    ##       "value_validation_type" "pairs" \
    ##       "value_validation_pairs" $j ] \
    ##     [ipx::get_user_parameters $ip_param -of_objects $cc]
    ##   }
    ## 
    ##   # FPGA info grup
    ##   set info_group_name "FPGA info"
    ##   set info_group [ipgui::get_groupspec -name $info_group_name -component $cc -quiet]
    ##   if { [string trim $info_group] eq "" } {
    ##     set page0 [ipgui::get_pagespec -name "Page 0" -component $cc]
    ##     set info_group [ipgui::add_group -name $info_group_name -component $cc \
    ##         -parent $page0 -display_name $info_group_name]
    ##   }
    ## 
    ##   set p [ipgui::get_guiparamspec -name $ip_param -component $cc]
    ##   set_property -dict [list "widget" "comboBox" ] $p
    ##   ipgui::move_param -component $cc -order 0 $p -parent $info_group
    ## }
    ## proc adi_if_define {name} {
    ## 
    ##   ipx::create_abstraction_definition analog.com interface ${name}_rtl 1.0
    ##   ipx::create_bus_definition analog.com interface $name 1.0
    ## 
    ##   set_property xml_file_name ${name}_rtl.xml [ipx::current_busabs]
    ##   set_property xml_file_name ${name}.xml [ipx::current_busdef]
    ##   set_property bus_type_vlnv analog.com:interface:${name}:1.0 [ipx::current_busabs]
    ## 
    ##   ipx::save_abstraction_definition [ipx::current_busabs]
    ##   ipx::save_bus_definition [ipx::current_busdef]
    ## }
    ## proc adi_if_ports {dir width name {type none}} {
    ## 
    ##   ipx::add_bus_abstraction_port $name [ipx::current_busabs]
    ##   set m_intf [ipx::get_bus_abstraction_ports $name -of_objects [ipx::current_busabs]]
    ##   set_property master_presence required $m_intf
    ##   set_property slave_presence  required $m_intf
    ##   set_property master_width $width $m_intf
    ##   set_property slave_width  $width $m_intf
    ## 
    ##   set m_dir "in"
    ##   set s_dir "out"
    ##   if {$dir eq "output"} {
    ##     set m_dir "out"
    ##     set s_dir "in"
    ##   }
    ## 
    ##   set_property master_direction $m_dir $m_intf
    ##   set_property slave_direction  $s_dir $m_intf
    ## 
    ##   if {$type ne "none"} {
    ##     set_property is_${type} true $m_intf
    ##   }
    ## 
    ##   ipx::save_bus_definition [ipx::current_busdef]
    ##   ipx::save_abstraction_definition [ipx::current_busabs]
    ## }
    ## proc adi_if_infer_bus {if_name mode name maps} {
    ## 
    ##   ipx::add_bus_interface $name [ipx::current_core]
    ##   set m_bus_if [ipx::get_bus_interfaces $name -of_objects [ipx::current_core]]
    ##   set_property abstraction_type_vlnv ${if_name}_rtl:1.0 $m_bus_if
    ##   set_property bus_type_vlnv ${if_name}:1.0 $m_bus_if
    ##   set_property interface_mode $mode $m_bus_if
    ## 
    ##   foreach map $maps  {
    ##     set m_maps [regexp -all -inline {\S+} $map]
    ##     lassign $m_maps p_name p_map
    ##     ipx::add_port_map $p_name $m_bus_if
    ##     set_property physical_name $p_map [ipx::get_port_maps $p_name -of_objects $m_bus_if]
    ##   }
    ## }
    # adi_ip_create ad_ip_jesd204_tpl_dac
    CRITICAL WARNING: vivado version mismatch; expected 2018.3, got 2019.1.
    ## set_msg_config -id {Vivado 12-1790} -string "Evaluation features should NOT be used in production systems." -new_severity WARNING
    ## set_msg_config -id {BD 41-1343} -new_severity WARNING
    ## set_msg_config -id {BD 41-1306} -new_severity WARNING
    ## set_msg_config -severity {CRITICAL WARNING} -quiet -id {BD 41-1276} -new_severity ERROR
    ## set_msg_config -id {IP_Flow 19-3656} -new_severity INFO
    ## set_msg_config -id {IP_Flow 19-4623} -new_severity INFO
    ## set_msg_config -id {IP_Flow 19-459} -new_severity INFO
    ## set_msg_config -id {Synth 8-3331} -new_severity INFO
    ## set_msg_config -id {Designutils 20-3303} -string "HDPYFinalizeIO" -new_severity INFO
    ## set_msg_config -id {Place 30-73} -string "axi_spi" -new_severity WARNING
    ## set_msg_config -string "PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY" -new_severity WARNING
    INFO: [IP_Flow 19-234] Refreshing IP repositories
    INFO: [IP_Flow 19-1700] Loaded user IP repository 'c:/cygwin64/home/dan5215/adi/hdl/library'.
    WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'c:/cygwin64/home/dan5215/adi/ghdl/library'; Can't find the specified path.
    If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
    INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/Xilinx/Vivado/2019.1/data/ip'.
    # adi_ip_files ad_ip_jesd204_tpl_dac [list \
    #   "$ad_hdl_dir/library/xilinx/common/ad_mul.v" \
    #   "$ad_hdl_dir/library/common/ad_dds_sine.v" \
    #   "$ad_hdl_dir/library/common/ad_dds_cordic_pipe.v" \
    #   "$ad_hdl_dir/library/common/ad_dds_sine_cordic.v" \
    #   "$ad_hdl_dir/library/common/ad_dds_2.v" \
    #   "$ad_hdl_dir/library/common/ad_dds_1.v" \
    #   "$ad_hdl_dir/library/common/ad_dds.v" \
    #   "$ad_hdl_dir/library/common/ad_perfect_shuffle.v" \
    #   "$ad_hdl_dir/library/common/ad_rst.v" \
    #   "$ad_hdl_dir/library/common/up_axi.v" \
    #   "$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
    #   "$ad_hdl_dir/library/common/up_xfer_status.v" \
    #   "$ad_hdl_dir/library/common/up_clock_mon.v" \
    #   "$ad_hdl_dir/library/common/up_dac_common.v" \
    #   "$ad_hdl_dir/library/common/up_dac_channel.v" \
    #   "$ad_hdl_dir/library/xilinx/common/up_xfer_cntrl_constr.xdc" \
    #   "$ad_hdl_dir/library/xilinx/common/ad_rst_constr.xdc" \
    #   "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \
    #   "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \
    #   "../ad_ip_jesd204_tpl_common/up_tpl_common.v" \
    #   "ad_ip_jesd204_tpl_dac_channel.v" \
    #   "ad_ip_jesd204_tpl_dac_core.v" \
    #   "ad_ip_jesd204_tpl_dac_framer.v" \
    #   "ad_ip_jesd204_tpl_dac_regmap.v" \
    #   "ad_ip_jesd204_tpl_dac_pn.v" \
    #   "ad_ip_jesd204_tpl_dac.v" ]
    # adi_ip_properties ad_ip_jesd204_tpl_dac
    INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/ad_dds.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/ad_dds_1.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/ad_dds_2.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/ad_dds_cordic_pipe.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/ad_dds_sine_cordic.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/ad_perfect_shuffle.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/ad_rst.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/up_axi.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/up_clock_mon.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/up_dac_channel.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/up_dac_common.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/up_xfer_status.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/xilinx/common/ad_rst_constr.xdc' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/xilinx/common/up_xfer_status_constr.xdc' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/xilinx/common/up_clock_mon_constr.xdc' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/ad_dds.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/ad_dds_1.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/ad_dds_2.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/ad_dds_cordic_pipe.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/ad_dds_sine.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/ad_dds_sine_cordic.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/xilinx/common/ad_mul.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/ad_perfect_shuffle.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/ad_rst.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/up_axi.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/up_clock_mon.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/up_dac_channel.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/up_dac_common.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_common/up_tpl_common.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/up_xfer_cntrl.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    INFO: [IP_Flow 19-459] IP file 'c:/cygwin64/home/dan5215/adi/hdl/library/common/up_xfer_status.v' appears to be outside of the project area 'c:/cygwin64/home/Dan5215/adi/hdl/library/jesd204/ad_ip_jesd204_tpl_dac'. You can use the ipx::package_project -import_files option to copy remote files into the IP directory.
    WARNING: [IP_Flow 19-5150] The Range '(NUM_CHANNELS - 1):0' is present in all ports of the interface 'dac'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port DATA on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'dac' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5464] No port map found for required logical port EN on bus interface abstraction fifo_rd_rtl for interface type slave.
    WARNING: [IP_Flow 19-5462] Defaulting to slave bus interface due to conflicts in bus interface inference.
    INFO: [IP_Flow 19-5107] Inferred bus interface 'link' of definition 'analog.com:interface:fifo_rd:1.0' (from User Repositories).
    WARNING: [IP_Flow 19-5150] The Range '(((NUM_LANES * 8) * OCTETS_PER_BEAT) - 1):0' is present in all ports of the interface 'link'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
    WARNING: [IP_Flow 19-5150] The Range '(NUM_CHANNELS - 1):0' is present in all ports of the interface 'interface_spi_engine_offload_ctrl'. It is assumed that this is meant to declare an array of interface. However, the IP Packager does not currently support Interface Arrays of variable length (based on a parameter). Please change the range to be a constant if you want IP Packager to infer this as an interface array.
    INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
    INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aresetn' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
    INFO: [IP_Flow 19-5107] Inferred bus interface 'link_clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
    INFO: [IP_Flow 19-5107] Inferred bus interface 's_axi_aclk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
    INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
    INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 's_axi'.
    INFO: [IP_Flow 19-4728] Bus Interface 's_axi_aclk': Added interface parameter 'ASSOCIATED_RESET' with value 's_axi_aresetn'.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac': A port map to the required logical port "DATA" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'dac': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-1965] Bus Interface 'link': A port map to the required logical port "EN" of the bus abstraction "analog.com:interface:fifo_rd_rtl:1.0" is missing.
    WARNING: [IP_Flow 19-3153] Bus Interface 'link_clk': ASSOCIATED_BUSIF bus parameter is missing.
    INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
    INFO: [IP_Flow 19-2187] The Product Guide file is missing.
    INFO: [IP_Flow 19-4623] Unrecognized family  azynquplus.  Please verify spelling and reissue command to set the supported files.
    INFO: [IP_Flow 19-4623] Unrecognized family  azynquplus.  Please verify spelling and reissue command to set the supported files.
    WARNING: [IP_Flow 19-1971] File named "../../../../../../dan5215/adi/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
    ERROR: [IP_Flow 19-851] Cannot find !C:/cygwin64/home/dan5215/adi/hdl/library/xilinx/common/up_xfer_cntrl_constr.xdc1! to reorder: "(null)".�
    ERROR: [Common 17-39] 'ipx::reorder_files' failed due to earlier errors.
    
        while executing
    "ipx::reorder_files -front $i_file $i_filegroup"
        ("foreach" body line 5)
        invoked from within
    "foreach i_file $ip_constr_files {
        set i_module [file tail $i_file]
        regsub {_constr\.xdc} $i_module {} i_module
        ipx::add_file $i_file $i_fi..."
        (procedure "adi_ip_properties_lite" line 31)
        invoked from within
    "adi_ip_properties_lite $ip_name"
        (procedure "adi_ip_properties" line 3)
        invoked from within
    "adi_ip_properties ad_ip_jesd204_tpl_dac"
        (file "ad_ip_jesd204_tpl_dac_ip.tcl" line 56)
    INFO: [Common 17-206] Exiting Vivado at Mon May 13 20:32:19 2024...
    

  • Hi, following up on this.  Any thoughts?

  • My guess is there is a tooling conflict. The hdl_2019_r1 branch requires Vivado 2018.3: https://github.com/analogdevicesinc/hdl/releases/tag/2019_r1

    If you want to use Vivado 2019.1, use the hdl_2019_r2 branch.

    -Travis

  • Ok, thanks.  That naming convention is very confusing.  So I changed to hdl_2019_r2, there is progress - now it was actually building stuff for a few minutes, but then it failed anyway at some other point.  See captures.  What is the issue now?

    ****** Vivado v2019.1 (64-bit)
      **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
      **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
        ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
    
    source system_project.tcl
    # source ../../scripts/adi_env.tcl
    ## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]]
    ## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]]
    ## if [info exists ::env(ADI_HDL_DIR)] {
    ##   set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)]
    ## }
    ## if [info exists ::env(ADI_GHDL_DIR)] {
    ##   set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)]
    ## }
    ## proc get_env_param {name default_value} {
    ##   if [info exists ::env($name)] {
    ##     puts "Getting from environment the parameter: $name=$::env($name) "
    ##     return $::env($name)
    ##   } else {
    ##     return $default_value
    ##   }
    ## }
    # source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
    ## if {![info exists REQUIRED_VIVADO_VERSION]} {
    ##   set REQUIRED_VIVADO_VERSION "2019.1"
    ## }
    ## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
    ##   set IGNORE_VERSION_CHECK 1
    ## } elseif {![info exists IGNORE_VERSION_CHECK]} {
    ##   set IGNORE_VERSION_CHECK 0
    ## }
    ## if {[info exists ::env(ADI_USE_OOC_SYNTHESIS)]} {
    ##   set ADI_USE_OOC_SYNTHESIS 1
    ## } elseif {![info exists ADI_USE_OOC_SYNTHESIS]} {
    ##   set ADI_USE_OOC_SYNTHESIS 0
    ## }
    ## set ADI_USE_INCR_COMP 1
    ## set ADI_POWER_OPTIMIZATION 0
    ## set p_board "not-applicable"
    ## set p_device "none"
    ## set sys_zynq 1
    ## set p_prcfg_init ""
    ## set p_prcfg_list ""
    ## set p_prcfg_status ""
    ## proc adi_project {project_name {mode 0} {parameter_list {}} } {
    ## 
    ##   global ad_hdl_dir
    ##   global ad_ghdl_dir
    ##   global p_board
    ##   global p_device
    ##   global sys_zynq
    ##   global REQUIRED_VIVADO_VERSION
    ##   global IGNORE_VERSION_CHECK
    ##   global ADI_USE_OOC_SYNTHESIS
    ##   global ADI_USE_INCR_COMP
    ## 
    ##   if [regexp "_ac701$" $project_name] {
    ##     set p_device "xc7a200tfbg676-2"
    ##     set p_board [lindex [lsearch -all -inline [get_board_parts] *ac701*] end]
    ##     set sys_zynq 0
    ##   }
    ##   if [regexp "_kc705$" $project_name] {
    ##     set p_device "xc7k325tffg900-2"
    ##     set p_board [lindex [lsearch -all -inline [get_board_parts] *kc705*] end]
    ##     set sys_zynq 0
    ##   }
    ##   if [regexp "_vc707$" $project_name] {
    ##     set p_device "xc7vx485tffg1761-2"
    ##     set p_board [lindex [lsearch -all -inline [get_board_parts] *vc707*] end]
    ##     set sys_zynq 0
    ##   }
    ##   if [regexp "_vcu118$" $project_name] {
    ##     set p_device "xcvu9p-flga2104-2L-e"
    ##     set p_board [lindex [lsearch -all -inline [get_board_parts] *vcu118*] end]
    ##     set sys_zynq 0
    ##   }
    ##   if [regexp "_kcu105$" $project_name] {
    ##     set p_device "xcku040-ffva1156-2-e"
    ##     set p_board [lindex [lsearch -all -inline [get_board_parts] *kcu105*] end]
    ##     set sys_zynq 0
    ##   }
    ##   if [regexp "_zed$" $project_name] {
    ##     set p_device "xc7z020clg484-1"
    ##     set p_board [lindex [lsearch -all -inline [get_board_parts] *zed*] end]
    ##     set sys_zynq 1
    ##   }
    ##   if [regexp "_coraz7s$" $project_name] {
    ##     set p_device "xc7z007sclg400-1"
    ##     set p_board "not-applicable"
    ##     set sys_zynq 1
    ##   }
    ##   if [regexp "_microzed$" $project_name] {
    ##     set p_device "xc7z010clg400-1"
    ##     set p_board "not-applicable"
    ##     set sys_zynq 1
    ##   }
    ##   if [regexp "_zc702$" $project_name] {
    ##     set p_device "xc7z020clg484-1"
    ##     set p_board [lindex [lsearch -all -inline [get_board_parts] *zc702*] end]
    ##     set sys_zynq 1
    ##   }
    ##   if [regexp "_zc706$" $project_name] {
    ##     set p_device "xc7z045ffg900-2"
    ##     set p_board [lindex [lsearch -all -inline [get_board_parts] *zc706*] end]
    ##     set sys_zynq 1
    ##   }
    ##   if [regexp "_mitx045$" $project_name] {
    ##     set p_device "xc7z045ffg900-2"
    ##     set p_board "not-applicable"
    ##     set sys_zynq 1
    ##   }
    ##   if [regexp "_zcu102$" $project_name] {
    ##     set p_device "xczu9eg-ffvb1156-2-e"
    ##     set p_board [lindex [lsearch -all -inline [get_board_parts] *zcu102*] end]
    ##     set sys_zynq 2
    ##   }
    ## 
    ##   set VIVADO_VERSION [version -short]
    ##   if {$IGNORE_VERSION_CHECK} {
    ##     if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
    ##       puts -nonewline "CRITICAL WARNING: vivado version mismatch; "
    ##       puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
    ##       puts -nonewline "got $VIVADO_VERSION.\n"
    ##     }
    ##   } else {
    ##     if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
    ##       puts -nonewline "ERROR: vivado version mismatch; "
    ##       puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
    ##       puts -nonewline "got $VIVADO_VERSION.\n"
    ##       puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n"
    ##       exit 2
    ##     }
    ##   }
    ## 
    ##   if {$mode == 0} {
    ##     set project_system_dir "./$project_name.srcs/sources_1/bd/system"
    ##     create_project $project_name . -part $p_device -force
    ##   } else {
    ##     set project_system_dir ".srcs/sources_1/bd/system"
    ##     create_project -in_memory -part $p_device
    ##   }
    ## 
    ##   if {$mode == 1} {
    ##     file mkdir $project_name.data
    ##   }
    ## 
    ##   if {$p_board ne "not-applicable"} {
    ##     set_property board_part $p_board [current_project]
    ##   }
    ## 
    ##   set lib_dirs $ad_hdl_dir/library
    ##   if {$ad_hdl_dir ne $ad_ghdl_dir} {
    ##     lappend lib_dirs $ad_ghdl_dir/library
    ##   }
    ## 
    ##   # Set a common IP cache for all projects
    ##   if {$ADI_USE_OOC_SYNTHESIS == 1} {
    ##     if {[file exists $ad_hdl_dir/ipcache] == 0} {
    ##       file mkdir $ad_hdl_dir/ipcache
    ##     }
    ##     config_ip_cache -import_from_project -use_cache_location $ad_hdl_dir/ipcache
    ##   }
    ## 
    ##   set_property ip_repo_paths $lib_dirs [current_fileset]
    ##   update_ip_catalog
    ## 
    ##   ## Load custom message severity definitions
    ##   source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl
    ## 
    ##   ## In Vivado there is a limit for the number of warnings and errors which are
    ##   ## displayed by the tool for a particular error or warning; the default value
    ##   ## of this limit is 100.
    ##   ## Overrides the default limit to 2000.
    ##   set_param messaging.defaultLimit 2000
    ## 
    ##   # Set parameters of the top level file
    ##   # Make the same parameters available to system_bd.tcl
    ##   set proj_params [get_property generic [current_fileset]]
    ##   foreach {param value} $parameter_list {
    ##     lappend proj_params $param=$value
    ##     set ad_project_params($param) $value
    ##   }
    ##   set_property generic $proj_params [current_fileset]
    ## 
    ##   create_bd_design "system"
    ##   source system_bd.tcl
    ## 
    ##   save_bd_design
    ##   validate_bd_design
    ## 
    ##   if {$ADI_USE_OOC_SYNTHESIS == 1} {
    ##     set_property synth_checkpoint_mode Hierarchical [get_files  $project_system_dir/system.bd]
    ##   } else {
    ##     set_property synth_checkpoint_mode None [get_files  $project_system_dir/system.bd]
    ##   }
    ##   generate_target {synthesis implementation} [get_files  $project_system_dir/system.bd]
    ##   if {$ADI_USE_OOC_SYNTHESIS == 1} {
    ##     export_ip_user_files -of_objects [get_files  $project_system_dir/system.bd] -no_script -sync -force -quiet
    ##     create_ip_run [get_files  $project_system_dir/system.bd]
    ##   }
    ##   make_wrapper -files [get_files $project_system_dir/system.bd] -top
    ## 
    ##   if {$mode == 0} {
    ##     import_files -force -norecurse -fileset sources_1 $project_system_dir/hdl/system_wrapper.v
    ##   } else {
    ##     write_hwdef -file "$project_name.data/$project_name.hwdef"
    ##   }
    ## 
    ##   if {$ADI_USE_INCR_COMP == 1} {
    ##     if {[file exists ./reference.dcp]} {
    ##       set_property incremental_checkpoint ./reference.dcp [get_runs impl_1]
    ##     }
    ##   }
    ## 
    ## }
    ## proc adi_project_files {project_name project_files} {
    ## 
    ##   foreach pfile $project_files {
    ##     if {[string range $pfile [expr 1 + [string last . $pfile]] end] == "xdc"} {
    ##       add_files -norecurse -fileset constrs_1 $pfile
    ##     } else {
    ##       add_files -norecurse -fileset sources_1 $pfile
    ##     }
    ##   }
    ## 
    ##   # NOTE: top file name is always system_top
    ##   set_property top system_top [current_fileset]
    ## }
    ## proc adi_project_run {project_name} {
    ## 
    ##   global ADI_POWER_OPTIMIZATION
    ##   global ADI_USE_OOC_SYNTHESIS
    ## 
    ##   if {$ADI_USE_OOC_SYNTHESIS == 1} {
    ##     launch_runs -jobs 4 system_*_synth_1 synth_1
    ##   } else {
    ##     launch_runs synth_1
    ##   }
    ##   wait_on_run synth_1
    ##   open_run synth_1
    ##   report_timing_summary -file timing_synth.log
    ## 
    ##   if {![info exists ::env(ADI_NO_BITSTREAM_COMPRESSION)] && ![info exists ADI_NO_BITSTREAM_COMPRESSION]} {
    ##     set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
    ##   }
    ## 
    ##   if {$ADI_POWER_OPTIMIZATION == 1} {
    ##   set_property STEPS.POWER_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
    ##   set_property STEPS.POST_PLACE_POWER_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
    ##   }
    ## 
    ##   launch_runs impl_1 -to_step write_bitstream
    ##   wait_on_run impl_1
    ##   open_run impl_1
    ##   report_timing_summary -warn_on_violation -file timing_impl.log
    ## 
    ##   if {[info exists ::env(ADI_GENERATE_UTILIZATION)]} {
    ##     set csv_file resource_utilization.csv
    ##     if {[ catch {
    ##       xilinx::designutils::report_failfast -csv -file $csv_file -transpose -no_header -ignore_pr -quiet
    ##       set MMCM [llength [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ *MMCM* }]]
    ##       set PLL [llength [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ *PLL* }]]
    ##       set worst_slack_setup [get_property SLACK [get_timing_paths -setup]]
    ##       set worst_slack_hold [get_property SLACK [get_timing_paths -hold]]
    ## 
    ##       set fileRead [open $csv_file r]
    ##       set lines [split [read $fileRead] "\n"]
    ##       set names_line [lindex $lines end-3]
    ##       set values_line [lindex $lines end-2]
    ##       close $fileRead
    ## 
    ##       set fileWrite [open $csv_file w]
    ##       puts $fileWrite "$names_line,MMCM*,PLL*,Worst_Setup_Slack,Worst_Hold_Slack"
    ##       puts $fileWrite "$values_line,$MMCM,$PLL,$worst_slack_setup,$worst_slack_hold"
    ##       close $fileWrite
    ##       } issue ] != 0 } {
    ##         puts "GENERATE_REPORTS: tclapp::xilinx::designutils not installed"
    ##       }
    ## 
    ##       # Define a list of IPs for which to generate report utilization
    ##       set IP_list {
    ##         ad_ip_jesd_204_tpl_adc
    ##         ad_ip_jesd_204_tpl_dac
    ##         axi_jesd204_rx
    ##         axi_jesd204_tx
    ##         jesd204_rx
    ##         jesd204_tx
    ##         axi_adxcvr
    ##         util_adxcvr
    ##         axi_dmac
    ##         util_cpack2
    ##         util_upack2
    ##       }
    ## 
    ##       foreach IP_name $IP_list {
    ## 	set output_file ${IP_name}_resource_utilization.log
    ##         file delete $output_file
    ##         foreach IP_instance [ get_cells -quiet -hierarchical -filter " ORIG_REF_NAME =~ $IP_name || REF_NAME =~ $IP_name " ] {
    ##           report_utilization -hierarchical -hierarchical_depth 1 -cells $IP_instance -file $output_file -append -quiet
    ##           report_property $IP_instance -file $output_file -append -quiet
    ##           set report_file [ open $output_file a ]
    ##           puts $report_file "\n\n\n"
    ##           close $report_file
    ##         }
    ##       }
    ##     } else {
    ##     puts "GENERATE_REPORTS: Resource utilization files won't be generated because ADI_GENERATE_UTILIZATION env var is not set"
    ##   }
    ## 
    ##   if {[info exists ::env(ADI_GENERATE_XPA)]} {
    ##     set csv_file power_analysis.csv
    ##     set Layers "8to11"
    ##     set CapLoad "20"
    ##     set ToggleRate "15.00000"
    ##     set StatProb "0.500000"
    ## 
    ##     set_load $CapLoad [all_outputs]
    ##     set_operating_conditions -board_layers $Layers
    ##     set_switching_activity -default_toggle_rate $ToggleRate
    ##     set_switching_activity -default_static_probability $StatProb
    ##     set_switching_activity -type lut -toggle_rate $ToggleRate -static_probability $StatProb -all
    ##     set_switching_activity -type register -toggle_rate $ToggleRate -static_probability $StatProb -all
    ##     set_switching_activity -type shift_register -toggle_rate $ToggleRate -static_probability $StatProb -all
    ##     set_switching_activity -type lut_ram -toggle_rate $ToggleRate -static_probability $StatProb -all
    ##     set_switching_activity -type bram -toggle_rate $ToggleRate -static_probability $StatProb -all
    ##     set_switching_activity -type dsp -toggle_rate $ToggleRate -static_probability $StatProb -all
    ##     set_switching_activity -type gt_rxdata -toggle_rate $ToggleRate -static_probability $StatProb -all
    ##     set_switching_activity -type gt_txdata -toggle_rate $ToggleRate -static_probability $StatProb -all
    ##     set_switching_activity -type io_output -toggle_rate $ToggleRate -static_probability $StatProb -all
    ##     set_switching_activity -type bram_enable -toggle_rate $ToggleRate -static_probability $StatProb -all
    ##     set_switching_activity -type bram_wr_enable -toggle_rate $ToggleRate -static_probability $StatProb -all
    ##     set_switching_activity -type io_bidir_enable -toggle_rate $ToggleRate -static_probability $StatProb -all
    ##     report_power -file $csv_file
    ## 
    ##     set fileRead [open $csv_file r]
    ##     set filecontent [read $fileRead]
    ##     set input_list [split $filecontent "\n"]
    ## 
    ##     set TextList [lsearch -all -inline $input_list "*Total On-Chip Power (W)*"]
    ##     set on_chip_pwr "[lindex [lindex $TextList 0] 6] W"
    ##     set TextList [lsearch -all -inline $input_list "*Junction Temperature (C)*"]
    ##     set junction_temp "[lindex [lindex $TextList 0] 5] *C"
    ##     close $fileRead
    ## 
    ##     set fileWrite [open $csv_file w]
    ##     puts $fileWrite "On-chip_power,Junction_temp"
    ##     puts $fileWrite "$on_chip_pwr,$junction_temp"
    ##     close $fileWrite
    ##   } else {
    ##     puts "GENERATE_REPORTS: Power analysis files won't be generated because ADI_GENERATE_XPA env var is not set"
    ##   }
    ## 
    ##   # Look for undefined clocks which do not show up in the timing summary
    ##   set timing_check [check_timing -override_defaults no_clock -no_header -return_string]
    ##   if {[regexp { (\d+) register} $timing_check -> num_regs]} {
    ## 
    ##     if {[info exist num_regs]} {
    ##       if {$num_regs > 0} {
    ##         puts "CRITICAL WARNING: There are $num_regs registers with no clocks !!! See no_clock.log for details."
    ##         check_timing -override_defaults no_clock -verbose -file no_clock.log
    ##       }
    ##     }
    ## 
    ##   } else {
    ##     puts "CRITICAL WARNING: The search for undefined clocks failed !!!"
    ##   }
    ## 
    ##   file mkdir $project_name.sdk
    ## 
    ##   set timing_string $[report_timing_summary -return_string]
    ##   if { [string match "*VIOLATED*" $timing_string] == 1 ||
    ##        [string match "*Timing constraints are not met*" $timing_string] == 1} {
    ##     file copy -force $project_name.runs/impl_1/system_top.sysdef $project_name.sdk/system_top_bad_timing.hdf
    ##     return -code error [format "ERROR: Timing Constraints NOT met!"]
    ##   } else {
    ##     file copy -force $project_name.runs/impl_1/system_top.sysdef $project_name.sdk/system_top.hdf
    ##   }
    ## }
    ## proc adi_project_synth {project_name prcfg_name hdl_files {xdc_files ""}} {
    ## 
    ##   global p_device
    ## 
    ##   set p_prefix "$project_name.data/$project_name"
    ## 
    ##   if {$prcfg_name eq ""} {
    ## 
    ##     read_verilog .srcs/sources_1/bd/system/hdl/system_wrapper.v
    ##     read_verilog $hdl_files
    ##     read_xdc $xdc_files
    ## 
    ##     synth_design -mode default -top system_top -part $p_device > $p_prefix.synth.rds
    ##     write_checkpoint -force $p_prefix.synth.dcp
    ##     close_project
    ## 
    ##   } else {
    ## 
    ##     create_project -in_memory -part $p_device
    ##     read_verilog $hdl_files
    ##     synth_design -mode out_of_context -top "prcfg" -part $p_device > $p_prefix.${prcfg_name}_synth.rds
    ##     write_checkpoint -force $p_prefix.${prcfg_name}_synth.dcp
    ##     close_project
    ##   }
    ## }
    ## proc adi_project_impl {project_name prcfg_name {xdc_files ""}} {
    ## 
    ##   global p_device
    ##   global p_prcfg_init
    ##   global p_prcfg_list
    ##   global p_prcfg_status
    ## 
    ##   set p_prefix "$project_name.data/$project_name"
    ## 
    ##   if {$prcfg_name eq "default"} {
    ##     set p_prcfg_status 0
    ##     set p_prcfg_list ""
    ##     set p_prcfg_init "$p_prefix.${prcfg_name}_impl.dcp"
    ##     file mkdir $project_name.sdk
    ##   }
    ## 
    ##   if {$prcfg_name eq "default"} {
    ## 
    ##     open_checkpoint $p_prefix.synth.dcp -part $p_device
    ##     read_xdc $xdc_files
    ##     read_checkpoint -cell i_prcfg $p_prefix.${prcfg_name}_synth.dcp
    ##     set_property HD.RECONFIGURABLE 1 [get_cells i_prcfg]
    ##     opt_design > $p_prefix.${prcfg_name}_opt.rds
    ##     write_debug_probes -force $p_prefix.${prcfg_name}_debug_nets.ltx
    ##     place_design > $p_prefix.${prcfg_name}_place.rds
    ##     route_design > $p_prefix.${prcfg_name}_route.rds
    ## 
    ##   } else {
    ## 
    ##     open_checkpoint $p_prefix.default_impl_bb.dcp -part $p_device
    ##     lock_design -level routing
    ##     read_checkpoint -cell i_prcfg $p_prefix.${prcfg_name}_synth.dcp
    ##     read_xdc $xdc_files
    ##     opt_design > $p_prefix.${prcfg_name}_opt.rds
    ##     place_design > $p_prefix.${prcfg_name}_place.rds
    ##     route_design > $p_prefix.${prcfg_name}_route.rds
    ##   }
    ## 
    ##   write_checkpoint -force $p_prefix.${prcfg_name}_impl.dcp
    ##   report_utilization -pblocks pb_prcfg -file $p_prefix.${prcfg_name}_utilization.rpt
    ##   report_timing_summary -file $p_prefix.${prcfg_name}_timing_summary.rpt
    ## 
    ##   if [expr [get_property SLACK [get_timing_paths]] < 0] {
    ##     set p_prcfg_status 1
    ##     puts "CRITICAL WARNING: Timing Constraints NOT met ($prcfg_name)!"
    ##   }
    ## 
    ##   write_checkpoint -force -cell i_prcfg $p_prefix.${prcfg_name}_prcfg_impl.dcp
    ##   update_design -cell i_prcfg -black_box
    ##   write_checkpoint -force $p_prefix.${prcfg_name}_impl_bb.dcp
    ##   open_checkpoint $p_prefix.${prcfg_name}_impl.dcp -part $p_device
    ##   write_bitstream -force -bin_file -file $p_prefix.${prcfg_name}.bit
    ##   write_sysdef -hwdef $p_prefix.hwdef -bitfile $p_prefix.${prcfg_name}.bit -file $p_prefix.${prcfg_name}.hdf
    ##   file copy -force $p_prefix.${prcfg_name}.hdf $project_name.sdk/system_top.${prcfg_name}.hdf
    ## 
    ##   if {$prcfg_name ne "default"} {
    ##     lappend p_prcfg_list "$p_prefix.${prcfg_name}_impl.dcp"
    ##   }
    ## 
    ##   if {$prcfg_name eq "default"} {
    ##     file copy -force $p_prefix.${prcfg_name}.hdf $project_name.sdk/system_top.hdf
    ##   }
    ## }
    ## proc adi_project_verify {project_name} {
    ## 
    ##   # checkpoint for the default design
    ##   global p_prcfg_init
    ##   # list of checkpoints with all the PRs integrated into the default design
    ##   global p_prcfg_list
    ##   global p_prcfg_status
    ## 
    ##   set p_prefix "$project_name.data/$project_name"
    ## 
    ##   pr_verify -full_check -initial $p_prcfg_init \
    ##     -additional $p_prcfg_list \
    ##     -file $p_prefix.prcfg_verify.log
    ## 
    ##   if {$p_prcfg_status == 1} {
    ##     return -code error [format "ERROR: Timing Constraints NOT met!"]
    ##   }
    ## }
    # source $ad_hdl_dir/projects/scripts/adi_board.tcl
    ## set sys_cpu_interconnect_index 0
    ## set sys_hp0_interconnect_index -1
    ## set sys_hp1_interconnect_index -1
    ## set sys_hp2_interconnect_index -1
    ## set sys_hp3_interconnect_index -1
    ## set sys_mem_interconnect_index -1
    ## set sys_mem_clk_index 0
    ## set xcvr_index -1
    ## set xcvr_tx_index 0
    ## set xcvr_rx_index 0
    ## set xcvr_instance NONE
    ## proc ad_ip_instance {i_ip i_name {i_params {}}} {
    ## 
    ##   set cell [create_bd_cell -type ip -vlnv [get_ipdefs -all -filter "VLNV =~ *:${i_ip}:* && \
    ##     design_tool_contexts =~ *IPI* && UPGRADE_VERSIONS == \"\""] ${i_name}]
    ##   if {$i_params != {}} {
    ##     set config {}
    ##     # Add CONFIG. prefix to all config options
    ##     foreach {k v} $i_params {
    ##       lappend config "CONFIG.$k" $v
    ##     }
    ##     set_property -dict $config $cell
    ##   }
    ## }
    ## proc ad_ip_parameter {i_name i_param i_value} {
    ## 
    ##   set_property ${i_param} ${i_value} [get_bd_cells ${i_name}]
    ## }
    ## proc ad_connect_type {p_name} {
    ## 
    ##   set m_name ""
    ## 
    ##   if {$m_name eq ""} {set m_name [get_bd_intf_pins  -quiet $p_name]}
    ##   if {$m_name eq ""} {set m_name [get_bd_pins       -quiet $p_name]}
    ##   if {$m_name eq ""} {set m_name [get_bd_intf_ports -quiet $p_name]}
    ##   if {$m_name eq ""} {set m_name [get_bd_ports      -quiet $p_name]}
    ##   if {$m_name eq ""} {set m_name [get_bd_intf_nets  -quiet $p_name]}
    ##   if {$m_name eq ""} {set m_name [get_bd_nets       -quiet $p_name]}
    ## 
    ##   return $m_name
    ## }
    ## proc ad_connect {p_name_1 p_name_2} {
    ## 
    ##   ## connect an IPI object to GND or VCC
    ##   ## instantiate xlconstant with the required width module if there isn't any
    ##   ## already
    ##   if {($p_name_2 eq "GND") || ($p_name_2 eq "VCC")} {
    ##     set p_size 1
    ##     set p_msb [get_property left [get_bd_pins $p_name_1]]
    ##     set p_lsb [get_property right [get_bd_pins $p_name_1]]
    ##     if {($p_msb ne "") && ($p_lsb ne "")} {
    ##       set p_size [expr (($p_msb + 1) - $p_lsb)]
    ##     }
    ##     set p_cell_name "$p_name_2\_$p_size"
    ##     if {[get_bd_cells -quiet $p_cell_name] eq ""} {
    ##       if {$p_name_2 eq "VCC"} {
    ##         set p_value [expr (1 << $p_size) - 1]
    ##       } else {
    ##         set p_value 0
    ##       }
    ##       ad_ip_instance xlconstant $p_cell_name
    ##       set_property CONFIG.CONST_WIDTH $p_size [get_bd_cells $p_cell_name]
    ##       set_property CONFIG.CONST_VAL $p_value [get_bd_cells $p_cell_name]
    ##     }
    ##     puts "connect_bd_net $p_cell_name/dout $p_name_1"
    ##     connect_bd_net [get_bd_pins $p_name_1] [get_bd_pins $p_cell_name/dout]
    ##     return
    ##   }
    ## 
    ##   set m_name_1 [ad_connect_type $p_name_1]
    ##   set m_name_2 [ad_connect_type $p_name_2]
    ## 
    ##   if {$m_name_1 eq ""} {
    ##     if {[get_property CLASS $m_name_2] eq "bd_intf_pin"} {
    ##       puts "create_bd_intf_net $p_name_1"
    ##       create_bd_intf_net $p_name_1
    ##     }
    ##     if {[get_property CLASS $m_name_2] eq "bd_pin"} {
    ##       puts "create_bd_net $p_name_1"
    ##       create_bd_net $p_name_1
    ##     }
    ##     set m_name_1 [ad_connect_type $p_name_1]
    ##   }
    ## 
    ##   if {[get_property CLASS $m_name_1] eq "bd_intf_pin"} {
    ##     puts "connect_bd_intf_net $m_name_1 $m_name_2"
    ##     connect_bd_intf_net $m_name_1 $m_name_2
    ##     return
    ##   }
    ## 
    ##   if {[get_property CLASS $m_name_1] eq "bd_pin"} {
    ##     puts "connect_bd_net $m_name_1 $m_name_2"
    ##     connect_bd_net $m_name_1 $m_name_2
    ##     return
    ##   }
    ## 
    ##   if {[get_property CLASS $m_name_1] eq "bd_net"} {
    ##     puts "connect_bd_net -net $m_name_1 $m_name_2"
    ##     connect_bd_net -net $m_name_1 $m_name_2
    ##     return
    ##   }
    ## }
    ## proc ad_disconnect {p_name_1 p_name_2} {
    ## 
    ##   set m_name_1 [ad_connect_type $p_name_1]
    ##   set m_name_2 [ad_connect_type $p_name_2]
    ## 
    ##   if {[get_property CLASS $m_name_1] eq "bd_net"} {
    ##     disconnect_bd_net $m_name_1 $m_name_2
    ##     return
    ##   }
    ## 
    ##   if {[get_property CLASS $m_name_1] eq "bd_port"} {
    ##     delete_bd_objs -quiet [get_bd_nets -quiet -of_objects \
    ##       [find_bd_objs -relation connected_to $m_name_1]]
    ##     delete_bd_objs -quiet $m_name_1
    ##     return
    ##   }
    ## 
    ##   if {[get_property CLASS $m_name_1] eq "bd_pin"} {
    ##     delete_bd_objs -quiet [get_bd_nets -quiet -of_objects \
    ##       [find_bd_objs -relation connected_to $m_name_1]]
    ##     delete_bd_objs -quiet $m_name_1
    ##     return
    ##   }
    ## }
    ## proc ad_xcvrcon {u_xcvr a_xcvr a_jesd {lane_map {}} {device_clk {}}} {
    ## 
    ##   global xcvr_index
    ##   global xcvr_tx_index
    ##   global xcvr_rx_index
    ##   global xcvr_instance
    ## 
    ##   set no_of_lanes [get_property CONFIG.NUM_OF_LANES [get_bd_cells $a_xcvr]]
    ##   set qpll_enable [get_property CONFIG.QPLL_ENABLE [get_bd_cells $a_xcvr]]
    ##   set tx_or_rx_n [get_property CONFIG.TX_OR_RX_N [get_bd_cells $a_xcvr]]
    ## 
    ##   set jesd204_bd_type [get_property TYPE [get_bd_cells $a_jesd]]
    ## 
    ##   if {$jesd204_bd_type == "hier"} {
    ##     set jesd204_type 0
    ##   } else {
    ##     set jesd204_type 1
    ##   }
    ## 
    ##   if {$xcvr_instance ne $u_xcvr} {
    ##     set xcvr_index [expr ($xcvr_index + 1)]
    ##     set xcvr_tx_index 0
    ##     set xcvr_rx_index 0
    ##     set xcvr_instance $u_xcvr
    ##   }
    ## 
    ##   set txrx "rx"
    ##   set data_dir "I"
    ##   set ctrl_dir "O"
    ##   set index $xcvr_rx_index
    ## 
    ##   if {$tx_or_rx_n == 1} {
    ## 
    ##     set txrx "tx"
    ##     set data_dir "O"
    ##     set ctrl_dir "I"
    ##     set index $xcvr_tx_index
    ##   }
    ## 
    ##   set m_sysref ${txrx}_sysref_${index}
    ##   set m_sync ${txrx}_sync_${index}
    ##   set m_data ${txrx}_data
    ## 
    ##   if {$xcvr_index >= 1} {
    ## 
    ##     set m_sysref ${txrx}_sysref_${xcvr_index}_${index}
    ##     set m_sync ${txrx}_sync_${xcvr_index}_${index}
    ##     set m_data ${txrx}_data_${xcvr_index}
    ##   }
    ## 
    ##   if {$jesd204_type == 0} {
    ##     set num_of_links [get_property CONFIG.NUM_LINKS [get_bd_cells $a_jesd/$txrx]]
    ##   } else {
    ##     set num_of_links 1
    ##   }
    ## 
    ##   create_bd_port -dir I $m_sysref
    ##   create_bd_port -from [expr $num_of_links - 1] -to 0 -dir ${ctrl_dir} $m_sync
    ## 
    ##   if {$device_clk == {}} {
    ##     set device_clk ${u_xcvr}/${txrx}_out_clk_${index}
    ##     set rst_gen [regsub -all "/" ${a_jesd}_rstgen "_"]
    ##     set create_rst_gen 1
    ##   } else {
    ##     set rst_gen ${device_clk}_rstgen
    ##     # Only create one reset gen per clock
    ##     set create_rst_gen [expr {[get_bd_cells -quiet ${rst_gen}] == {}}]
    ##   }
    ## 
    ##   if {${create_rst_gen}} {
    ##     ad_ip_instance proc_sys_reset ${rst_gen}
    ##     ad_connect ${device_clk} ${rst_gen}/slowest_sync_clk
    ##     ad_connect sys_cpu_resetn ${rst_gen}/ext_reset_in
    ##   }
    ## 
    ##   for {set n 0} {$n < $no_of_lanes} {incr n} {
    ## 
    ##     set m [expr ($n + $index)]
    ## 
    ## 
    ##     if {$lane_map != {}} {
    ##       set phys_lane [lindex $lane_map $n]
    ##     } else {
    ##       set phys_lane $m
    ##     }
    ## 
    ##     if {$tx_or_rx_n == 0} {
    ##       ad_connect  ${a_xcvr}/up_es_${n} ${u_xcvr}/up_es_${phys_lane}
    ##       if {$jesd204_type == 0} {
    ##         ad_connect  ${a_jesd}/phy_en_char_align ${u_xcvr}/${txrx}_calign_${phys_lane}
    ##       } else {
    ##         ad_connect  ${a_jesd}/rxencommaalign_out ${u_xcvr}/${txrx}_calign_${phys_lane}
    ##       }
    ##     }
    ## 
    ##     if {(($n%4) == 0) && ($qpll_enable == 1)} {
    ##       ad_connect  ${a_xcvr}/up_cm_${n} ${u_xcvr}/up_cm_${n}
    ##     }
    ##     ad_connect  ${a_xcvr}/up_ch_${n} ${u_xcvr}/up_${txrx}_${phys_lane}
    ##     ad_connect  ${device_clk} ${u_xcvr}/${txrx}_clk_${phys_lane}
    ##     if {$phys_lane != {}} {
    ##       if {$jesd204_type == 0} {
    ##         ad_connect  ${u_xcvr}/${txrx}_${phys_lane} ${a_jesd}/${txrx}_phy${n}
    ##       } else {
    ##         ad_connect  ${u_xcvr}/${txrx}_${phys_lane} ${a_jesd}/gt${n}_${txrx}
    ##       }
    ##     }
    ## 
    ##     create_bd_port -dir ${data_dir} ${m_data}_${m}_p
    ##     create_bd_port -dir ${data_dir} ${m_data}_${m}_n
    ##     ad_connect  ${u_xcvr}/${txrx}_${m}_p ${m_data}_${m}_p
    ##     ad_connect  ${u_xcvr}/${txrx}_${m}_n ${m_data}_${m}_n
    ##   }
    ## 
    ##   if {$jesd204_type == 0} {
    ##     ad_connect  ${a_jesd}/sysref $m_sysref
    ##     ad_connect  ${a_jesd}/sync $m_sync
    ##     ad_connect  ${device_clk} ${a_jesd}/device_clk
    ##   } else {
    ##     ad_connect  ${a_jesd}/${txrx}_sysref $m_sysref
    ##     ad_connect  ${a_jesd}/${txrx}_sync $m_sync
    ##     ad_connect  ${device_clk} ${a_jesd}/${txrx}_core_clk
    ##     ad_connect  ${a_xcvr}/up_status ${a_jesd}/${txrx}_reset_done
    ##     ad_connect  ${rst_gen}/peripheral_reset ${a_jesd}/${txrx}_reset
    ##   }
    ## 
    ##   if {$tx_or_rx_n == 0} {
    ##     set xcvr_rx_index [expr ($xcvr_rx_index + $no_of_lanes)]
    ##   }
    ## 
    ##   if {$tx_or_rx_n == 1} {
    ##     set xcvr_tx_index [expr ($xcvr_tx_index + $no_of_lanes)]
    ##   }
    ## }
    ## proc ad_xcvrpll {m_src m_dst} {
    ## 
    ##   foreach p_dst [get_bd_pins -quiet $m_dst] {
    ##     connect_bd_net [ad_connect_type $m_src] $p_dst
    ##   }
    ## }
    ## proc ad_mem_hp0_interconnect {p_clk p_name} {
    ## 
    ##   global sys_zynq
    ## 
    ##   if {($sys_zynq == 0) && ($p_name eq "sys_ps7/S_AXI_HP0")} {return}
    ##   if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
    ##   if {$sys_zynq >= 1} {ad_mem_hpx_interconnect "HP0" $p_clk $p_name}
    ## }
    ## proc ad_mem_hp1_interconnect {p_clk p_name} {
    ## 
    ##   global sys_zynq
    ## 
    ##   if {($sys_zynq == 0) && ($p_name eq "sys_ps7/S_AXI_HP1")} {return}
    ##   if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
    ##   if {$sys_zynq >= 1} {ad_mem_hpx_interconnect "HP1" $p_clk $p_name}
    ## }
    ## proc ad_mem_hp2_interconnect {p_clk p_name} {
    ## 
    ##   global sys_zynq
    ## 
    ##   if {($sys_zynq == 0) && ($p_name eq "sys_ps7/S_AXI_HP2")} {return}
    ##   if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
    ##   if {$sys_zynq >= 1} {ad_mem_hpx_interconnect "HP2" $p_clk $p_name}
    ## }
    ## proc ad_mem_hp3_interconnect {p_clk p_name} {
    ## 
    ##   global sys_zynq
    ## 
    ##   if {($sys_zynq == 0) && ($p_name eq "sys_ps7/S_AXI_HP3")} {return}
    ##   if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
    ##   if {$sys_zynq >= 1} {ad_mem_hpx_interconnect "HP3" $p_clk $p_name}
    ## }
    ## proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
    ## 
    ##   global sys_zynq
    ##   global sys_ddr_addr_seg
    ##   global sys_hp0_interconnect_index
    ##   global sys_hp1_interconnect_index
    ##   global sys_hp2_interconnect_index
    ##   global sys_hp3_interconnect_index
    ##   global sys_mem_interconnect_index
    ##   global sys_mem_clk_index
    ## 
    ##   set p_name_int $p_name
    ##   set p_clk_source [get_bd_pins -filter {DIR == O} -of_objects [get_bd_nets $p_clk]]
    ## 
    ##   if {$p_sel eq "MEM"} {
    ##     if {$sys_mem_interconnect_index < 0} {
    ##       ad_ip_instance smartconnect axi_mem_interconnect
    ##     }
    ##     set m_interconnect_index $sys_mem_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_mem_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs -of_objects [get_bd_cells axi_ddr_cntrl]]
    ##   }
    ## 
    ##   if {($p_sel eq "HP0") && ($sys_zynq == 1)} {
    ##     if {$sys_hp0_interconnect_index < 0} {
    ##       set p_name_int sys_ps7/S_AXI_HP0
    ##       set_property CONFIG.PCW_USE_S_AXI_HP0 {1} [get_bd_cells sys_ps7]
    ##       ad_ip_instance smartconnect axi_hp0_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hp0_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hp0_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP0/HP0_DDR_LOWOCM]
    ##   }
    ## 
    ##   if {($p_sel eq "HP1") && ($sys_zynq == 1)} {
    ##     if {$sys_hp1_interconnect_index < 0} {
    ##       set p_name_int sys_ps7/S_AXI_HP1
    ##       set_property CONFIG.PCW_USE_S_AXI_HP1 {1} [get_bd_cells sys_ps7]
    ##       ad_ip_instance smartconnect axi_hp1_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hp1_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hp1_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM]
    ##   }
    ## 
    ##   if {($p_sel eq "HP2") && ($sys_zynq == 1)} {
    ##     if {$sys_hp2_interconnect_index < 0} {
    ##       set p_name_int sys_ps7/S_AXI_HP2
    ##       set_property CONFIG.PCW_USE_S_AXI_HP2 {1} [get_bd_cells sys_ps7]
    ##       ad_ip_instance smartconnect axi_hp2_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hp2_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hp2_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM]
    ##   }
    ## 
    ##   if {($p_sel eq "HP3") && ($sys_zynq == 1)} {
    ##     if {$sys_hp3_interconnect_index < 0} {
    ##       set p_name_int sys_ps7/S_AXI_HP3
    ##       set_property CONFIG.PCW_USE_S_AXI_HP3 {1} [get_bd_cells sys_ps7]
    ##       ad_ip_instance smartconnect axi_hp3_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hp3_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hp3_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM]
    ##   }
    ## 
    ##   if {($p_sel eq "HP0") && ($sys_zynq == 2)} {
    ##     if {$sys_hp0_interconnect_index < 0} {
    ##       set p_name_int sys_ps8/S_AXI_HP0_FPD
    ##       set_property CONFIG.PSU__USE__S_AXI_GP2 {1} [get_bd_cells sys_ps8]
    ##       ad_ip_instance smartconnect axi_hp0_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hp0_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hp0_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps8/SAXIGP2/HP0_DDR_*]
    ##   }
    ## 
    ##   if {($p_sel eq "HP1") && ($sys_zynq == 2)} {
    ##     if {$sys_hp1_interconnect_index < 0} {
    ##       set p_name_int sys_ps8/S_AXI_HP1_FPD
    ##       set_property CONFIG.PSU__USE__S_AXI_GP3 {1} [get_bd_cells sys_ps8]
    ##       ad_ip_instance smartconnect axi_hp1_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hp1_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hp1_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps8/SAXIGP3/HP1_DDR_*]
    ##   }
    ## 
    ##   if {($p_sel eq "HP2") && ($sys_zynq == 2)} {
    ##     if {$sys_hp2_interconnect_index < 0} {
    ##       set p_name_int sys_ps8/S_AXI_HP2_FPD
    ##       set_property CONFIG.PSU__USE__S_AXI_GP4 {1} [get_bd_cells sys_ps8]
    ##       ad_ip_instance smartconnect axi_hp2_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hp2_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hp2_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps8/SAXIGP4/HP2_DDR_*]
    ##   }
    ## 
    ##   if {($p_sel eq "HP3") && ($sys_zynq == 2)} {
    ##     if {$sys_hp3_interconnect_index < 0} {
    ##       set p_name_int sys_ps8/S_AXI_HP3_FPD
    ##       set_property CONFIG.PSU__USE__S_AXI_GP5 {1} [get_bd_cells sys_ps8]
    ##       ad_ip_instance smartconnect axi_hp3_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hp3_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hp3_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps8/SAXIGP5/HP3_DDR_*]
    ##   }
    ## 
    ##   set i_str "S$m_interconnect_index"
    ##   if {$m_interconnect_index < 10} {
    ##     set i_str "S0$m_interconnect_index"
    ##   }
    ## 
    ##   set m_interconnect_index [expr $m_interconnect_index + 1]
    ## 
    ##   set p_intf_name [lrange [split $p_name_int "/"] end end]
    ##   set p_cell_name [lrange [split $p_name_int "/"] 0 0]
    ##   set p_intf_clock [get_bd_pins -filter "TYPE == clk && (CONFIG.ASSOCIATED_BUSIF == ${p_intf_name} || \
    ##     CONFIG.ASSOCIATED_BUSIF =~ ${p_intf_name}:* || CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name} || \
    ##     CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name}:*)" -quiet -of_objects [get_bd_cells $p_cell_name]]
    ##   if {[find_bd_objs -quiet -relation connected_to $p_intf_clock] ne "" ||
    ##       $p_intf_clock eq $p_clk_source} {
    ##     set p_intf_clock ""
    ##   }
    ## 
    ##   regsub clk $p_clk resetn p_rst
    ##   if {[get_bd_nets -quiet $p_rst] eq ""} {
    ##     set p_rst sys_cpu_resetn
    ##   }
    ## 
    ##   if {$m_interconnect_index == 0} {
    ##     set_property CONFIG.NUM_MI 1 $m_interconnect_cell
    ##     set_property CONFIG.NUM_SI 1 $m_interconnect_cell
    ##     ad_connect $p_rst $m_interconnect_cell/ARESETN
    ##     ad_connect $p_clk $m_interconnect_cell/ACLK
    ##     ad_connect $m_interconnect_cell/M00_AXI $p_name_int
    ##     if {$p_intf_clock ne ""} {
    ##       ad_connect $p_clk $p_intf_clock
    ##     }
    ##   } else {
    ## 
    ##     set_property CONFIG.NUM_SI $m_interconnect_index $m_interconnect_cell
    ##     if {[lsearch [get_bd_nets -of_object [get_bd_pins $m_interconnect_cell/ACLK*]] [get_bd_nets $p_clk]] == -1 } {
    ##         incr sys_mem_clk_index
    ##         set_property CONFIG.NUM_CLKS [expr $sys_mem_clk_index +1] $m_interconnect_cell
    ##         ad_connect $p_clk $m_interconnect_cell/ACLK$sys_mem_clk_index
    ##     }
    ##     ad_connect $m_interconnect_cell/${i_str}_AXI $p_name_int
    ##     if {$p_intf_clock ne ""} {
    ##       ad_connect $p_clk $p_intf_clock
    ##     }
    ## 
    ##     set mem_mapped [get_bd_addr_segs -of [get_bd_addr_spaces -of  [get_bd_intf_pins -filter {NAME=~ *DLMB*} -of [get_bd_cells /sys_mb]]] -filter {NAME=~ *DDR* || NAME=~ *ddr*}]
    ## 
    ##     if {$mem_mapped eq ""} {
    ##       assign_bd_address $m_addr_seg
    ##     } else {
    ##       assign_bd_address -offset [get_property OFFSET $mem_mapped] \
    ##                         -range  [get_property RANGE $mem_mapped] $m_addr_seg
    ##     }
    ##   }
    ## 
    ##   if {$p_sel eq "MEM"} {set sys_mem_interconnect_index $m_interconnect_index}
    ##   if {$p_sel eq "HP0"} {set sys_hp0_interconnect_index $m_interconnect_index}
    ##   if {$p_sel eq "HP1"} {set sys_hp1_interconnect_index $m_interconnect_index}
    ##   if {$p_sel eq "HP2"} {set sys_hp2_interconnect_index $m_interconnect_index}
    ##   if {$p_sel eq "HP3"} {set sys_hp3_interconnect_index $m_interconnect_index}
    ## 
    ## }
    ## proc ad_cpu_interconnect {p_address p_name} {
    ## 
    ##   global sys_zynq
    ##   global sys_cpu_interconnect_index
    ## 
    ##   set i_str "M$sys_cpu_interconnect_index"
    ##   if {$sys_cpu_interconnect_index < 10} {
    ##     set i_str "M0$sys_cpu_interconnect_index"
    ##   }
    ## 
    ##   if {$sys_cpu_interconnect_index == 0} {
    ##     ad_ip_instance axi_interconnect axi_cpu_interconnect
    ##     if {$sys_zynq == 2} {
    ##       ad_connect sys_cpu_clk sys_ps8/maxihpm0_lpd_aclk
    ##       ad_connect sys_cpu_clk axi_cpu_interconnect/ACLK
    ##       ad_connect sys_cpu_clk axi_cpu_interconnect/S00_ACLK
    ##       ad_connect sys_cpu_resetn axi_cpu_interconnect/ARESETN
    ##       ad_connect sys_cpu_resetn axi_cpu_interconnect/S00_ARESETN
    ##       ad_connect axi_cpu_interconnect/S00_AXI sys_ps8/M_AXI_HPM0_LPD
    ##     }
    ##     if {$sys_zynq == 1} {
    ##       ad_connect sys_cpu_clk sys_ps7/M_AXI_GP0_ACLK
    ##       ad_connect sys_cpu_clk axi_cpu_interconnect/ACLK
    ##       ad_connect sys_cpu_clk axi_cpu_interconnect/S00_ACLK
    ##       ad_connect sys_cpu_resetn axi_cpu_interconnect/ARESETN
    ##       ad_connect sys_cpu_resetn axi_cpu_interconnect/S00_ARESETN
    ##       ad_connect axi_cpu_interconnect/S00_AXI sys_ps7/M_AXI_GP0
    ##     }
    ##     if {$sys_zynq == 0} {
    ##       ad_connect sys_cpu_clk axi_cpu_interconnect/ACLK
    ##       ad_connect sys_cpu_clk axi_cpu_interconnect/S00_ACLK
    ##       ad_connect sys_cpu_resetn axi_cpu_interconnect/ARESETN
    ##       ad_connect sys_cpu_resetn axi_cpu_interconnect/S00_ARESETN
    ##       ad_connect axi_cpu_interconnect/S00_AXI sys_mb/M_AXI_DP
    ##     }
    ##   }
    ## 
    ##   if {$sys_zynq == 2} {
    ##     set sys_addr_cntrl_space [get_bd_addr_spaces sys_ps8/Data]
    ##   }
    ##   if {$sys_zynq == 1} {
    ##     set sys_addr_cntrl_space [get_bd_addr_spaces sys_ps7/Data]
    ##   }
    ##   if {$sys_zynq == 0} {
    ##     set sys_addr_cntrl_space [get_bd_addr_spaces sys_mb/Data]
    ##   }
    ## 
    ##   set sys_cpu_interconnect_index [expr $sys_cpu_interconnect_index + 1]
    ## 
    ## 
    ##   set p_cell [get_bd_cells $p_name]
    ##   set p_intf [get_bd_intf_pins -filter "MODE == Slave && VLNV == xilinx.com:interface:aximm_rtl:1.0"\
    ##     -of_objects $p_cell]
    ## 
    ##   set p_hier_cell $p_cell
    ##   set p_hier_intf $p_intf
    ## 
    ##   while {$p_hier_intf != "" && [get_property TYPE $p_hier_cell] == "hier"} {
    ##     set p_hier_intf [find_bd_objs -boundary_type lower \
    ##       -relation connected_to $p_hier_intf]
    ##     if {$p_hier_intf != {}} {
    ##       set p_hier_cell [get_bd_cells -of_objects $p_hier_intf]
    ##     } else {
    ##       set p_hier_cell {}
    ##     }
    ##   }
    ## 
    ##   set p_intf_clock ""
    ##   set p_intf_reset ""
    ## 
    ##   if {$p_hier_cell != {}} {
    ##     set p_intf_name [lrange [split $p_hier_intf "/"] end end]
    ## 
    ##     set p_intf_clock [get_bd_pins -filter "TYPE == clk && \
    ##       (CONFIG.ASSOCIATED_BUSIF == ${p_intf_name} || \
    ##       CONFIG.ASSOCIATED_BUSIF =~ ${p_intf_name}:* || \
    ##       CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name} || \
    ##       CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name}:*)" \
    ##       -quiet -of_objects $p_hier_cell]
    ##     set p_intf_reset [get_bd_pins -filter "TYPE == rst && \
    ##       (CONFIG.ASSOCIATED_BUSIF == ${p_intf_name} || \
    ##        CONFIG.ASSOCIATED_BUSIF =~ ${p_intf_name}:* ||
    ##        CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name} || \
    ##        CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name}:*)" \
    ##        -quiet -of_objects $p_hier_cell]
    ## 
    ##     if {($p_intf_clock ne "") && ($p_intf_reset eq "")} {
    ##       set p_intf_reset [get_property CONFIG.ASSOCIATED_RESET [get_bd_pins ${p_intf_clock}]]
    ##       if {$p_intf_reset ne ""} {
    ##         set p_intf_reset [get_bd_pins -filter "NAME == $p_intf_reset" -of_objects $p_hier_cell]
    ##       }
    ##     }
    ## 
    ##     # Trace back up
    ##     set p_hier_cell2 $p_hier_cell
    ## 
    ##     while {$p_intf_clock != {} && $p_hier_cell2 != $p_cell && $p_hier_cell2 != {}} {
    ##       puts $p_intf_clock
    ##       puts $p_hier_cell2
    ##       set p_intf_clock [find_bd_objs -boundary_type upper \
    ##         -relation connected_to $p_intf_clock]
    ##       if {$p_intf_clock != {}} {
    ##         set p_intf_clock [get_bd_pins [get_property PATH $p_intf_clock]]
    ##         set p_hier_cell2 [get_bd_cells -of_objects $p_intf_clock]
    ##       }
    ##     }
    ## 
    ##     set p_hier_cell2 $p_hier_cell
    ## 
    ##     while {$p_intf_reset != {} && $p_hier_cell2 != $p_cell && $p_hier_cell2 != {}} {
    ##       set p_intf_reset [find_bd_objs -boundary_type upper \
    ##         -relation connected_to $p_intf_reset]
    ##       if {$p_intf_reset != {}} {
    ##         set p_intf_reset [get_bd_pins [get_property PATH $p_intf_reset]]
    ##         set p_hier_cell2 [get_bd_cells -of_objects $p_intf_reset]
    ##       }
    ##     }
    ##   }
    ## 
    ## 
    ##   if {[find_bd_objs -quiet -relation connected_to $p_intf_clock] ne ""} {
    ##     set p_intf_clock ""
    ##   }
    ##   if {$p_intf_reset ne ""} {
    ##     if {[find_bd_objs -quiet -relation connected_to $p_intf_reset] ne ""} {
    ##       set p_intf_reset ""
    ##     }
    ##   }
    ## 
    ##   set_property CONFIG.NUM_MI $sys_cpu_interconnect_index [get_bd_cells axi_cpu_interconnect]
    ## 
    ##   ad_connect sys_cpu_clk axi_cpu_interconnect/${i_str}_ACLK
    ##   if {$p_intf_clock ne ""} {
    ##     ad_connect sys_cpu_clk ${p_intf_clock}
    ##   }
    ##   ad_connect sys_cpu_resetn axi_cpu_interconnect/${i_str}_ARESETN
    ##   if {$p_intf_reset ne ""} {
    ##     ad_connect sys_cpu_resetn ${p_intf_reset}
    ##   }
    ##   ad_connect axi_cpu_interconnect/${i_str}_AXI ${p_intf}
    ## 
    ##   set p_seg [get_bd_addr_segs -of_objects $p_hier_cell]
    ##   set p_index 0
    ##   foreach p_seg_name $p_seg {
    ##     if {$p_index == 0} {
    ##       set p_seg_range [get_property range $p_seg_name]
    ##       if {$p_seg_range < 0x1000} {
    ##         set p_seg_range 0x1000
    ##       }
    ##       if {$sys_zynq == 2} {
    ##         if {($p_address >= 0x40000000) && ($p_address <= 0x4fffffff)} {
    ##           set p_address [expr ($p_address + 0x40000000)]
    ##         }
    ##         if {($p_address >= 0x70000000) && ($p_address <= 0x7fffffff)} {
    ##           set p_address [expr ($p_address + 0x20000000)]
    ##         }
    ##       }
    ##       create_bd_addr_seg -range $p_seg_range \
    ##         -offset $p_address $sys_addr_cntrl_space \
    ##         $p_seg_name "SEG_data_${p_name}"
    ##     } else {
    ##       assign_bd_address $p_seg_name
    ##     }
    ##     incr p_index
    ##   }
    ## }
    ## proc ad_cpu_interrupt {p_ps_index p_mb_index p_name} {
    ## 
    ##   global sys_zynq
    ## 
    ##   if {$sys_zynq == 0} {set p_index_int $p_mb_index}
    ##   if {$sys_zynq >= 1} {set p_index_int $p_ps_index}
    ## 
    ##   set p_index [regsub -all {[^0-9]} $p_index_int ""]
    ##   set m_index [expr ($p_index - 8)]
    ## 
    ##   if {($sys_zynq == 2) && ($p_index <= 7)} {
    ##     set p_net [get_bd_nets -of_objects [get_bd_pins sys_concat_intc_0/In$p_index]]
    ##     set p_pin [get_bd_pins sys_concat_intc_0/In$p_index]
    ## 
    ##     puts "disconnect_bd_net $p_net $p_pin"
    ##     disconnect_bd_net $p_net $p_pin
    ##     ad_connect sys_concat_intc_0/In$p_index $p_name
    ##   }
    ## 
    ##   if {($sys_zynq == 2) && ($p_index >= 8)} {
    ##     set p_net [get_bd_nets -of_objects [get_bd_pins sys_concat_intc_1/In$m_index]]
    ##     set p_pin [get_bd_pins sys_concat_intc_1/In$m_index]
    ## 
    ##     puts "disconnect_bd_net $p_net $p_pin"
    ##     disconnect_bd_net $p_net $p_pin
    ##     ad_connect sys_concat_intc_1/In$m_index $p_name
    ##   }
    ## 
    ##   if {$sys_zynq <= 1} {
    ## 
    ##     set p_net [get_bd_nets -of_objects [get_bd_pins sys_concat_intc/In$p_index]]
    ##     set p_pin [get_bd_pins sys_concat_intc/In$p_index]
    ## 
    ##     puts "disconnect_bd_net $p_net $p_pin"
    ##     disconnect_bd_net $p_net $p_pin
    ##     ad_connect sys_concat_intc/In$p_index $p_name
    ##   }
    ## }
    ## proc stringtohex {str blocksize} {
    ##   binary scan $str H* hex
    ##   return [format %0-[expr $blocksize * 2]s $hex]
    ## }
    ## proc checksum8bit {hex} {
    ## 
    ##   set chks 0
    ##   for {set i 0} {$i < [string length $hex]} {incr i} {
    ##     if { ($i+1) % 2 == 0} {
    ##       set chks [expr $chks + "0x[string range $hex $i-1 $i]"]
    ##     }
    ##   }
    ##   return [format %0.2x [expr 255 - [expr "0x[string range [format %0.2x $chks] [expr [string length [format %0.2x $chks]] -2] [expr [string length [format %0.2x $chks]] -1]]"] +1]]
    ## }
    ## proc hexstr_flip {str} {
    ## 
    ##   set fstr {}
    ##   for {set i 0} {$i < [string length $str]} {incr i} {
    ##     if { ($i+1) % 8 == 0} {
    ##       set line [string range $str [expr $i - 7] $i]
    ##       set fline {}
    ##       for {set j 0} {$j < [string length $line]} {incr j} {
    ##         if { ($j+1) % 2 == 0} {
    ##           append fline [string reverse [append byte [string index $line $j]]]
    ##         } else {
    ##           set byte [string index $line $j]
    ##         }
    ##       }
    ##       append fstr [string reverse $fline]
    ##     }
    ##   }
    ##   return $fstr
    ## }
    ## proc sysid_gen_sys_init_file {{custom_string {}}} {
    ## 
    ##   # git sha
    ##   if {[catch {exec git rev-parse HEAD} gitsha_string] != 0} {
    ##     set gitsha_string 0
    ##   }
    ##   set gitsha_hex [hexstr_flip [stringtohex $gitsha_string 44]]
    ## 
    ##   #git clean
    ##   set git_clean_string "f"
    ##   if {$gitsha_string != 0} {
    ##     if {[catch {exec git status .} gitstat_string] == 0} {
    ##       if [expr [string match *modified $gitstat_string] == 0] {
    ##         set git_clean_string "t"
    ##       }
    ##     }
    ##   }
    ##   set git_clean_hex [hexstr_flip [stringtohex $git_clean_string 4]]
    ## 
    ##   # vadj check
    ##   set vadj_check_string "vadj"
    ##   set vadj_check_hex [hexstr_flip [stringtohex $vadj_check_string 4]]
    ## 
    ##   # time and date
    ##   set thetime [clock seconds]
    ##   set timedate_hex [hexstr_flip [stringtohex $thetime 12]]
    ## 
    ##   # merge components
    ##   set verh_hex {}
    ##   set verh_size 448
    ## 
    ##   append verh_hex $gitsha_hex $git_clean_hex $vadj_check_hex $timedate_hex
    ##   append verh_hex "00000000" [checksum8bit $verh_hex] "000000"
    ##   set verh_hex [format %0-[expr [expr $verh_size] * 8]s $verh_hex]
    ## 
    ##   # common header
    ##   # size in lines
    ##   set table_size 16
    ##   set comh_size [expr 8 * $table_size]
    ## 
    ##   # set version
    ##   set comh_ver_hex "00000001"
    ## 
    ##   set boardname [lindex [split [current_project] _] [expr [llength [split [current_project] _]] - 1]]
    ## 
    ##   # board name
    ##   set boardname_hex [hexstr_flip [stringtohex $boardname 32]]
    ##   
    ##   # project name
    ##   set projname_hex [hexstr_flip [stringtohex [string trimright [string trimright [current_project] $boardname] _] 32]]
    ## 
    ##   # custom string
    ##   set custom_hex [hexstr_flip [stringtohex $custom_string 64]]
    ## 
    ##   # pr offset
    ##   # not used
    ##   set pr_offset "00000000"
    ## 
    ##   # init - generate header
    ##   set comh_hex {}
    ##   append comh_hex $comh_ver_hex
    ## 
    ##   # offset for internal use area
    ##   set offset $table_size
    ##   append comh_hex [format %08s [format %0.2x $offset]]
    ## 
    ##   # offset for projname_hex
    ##   set offset [expr $table_size + $verh_size]
    ##   append comh_hex [format %08s [format %0.2x $offset]]
    ## 
    ##   # offset for boardname_hex
    ##   set offset [expr $offset + [expr [string length $projname_hex] / 8]]
    ##   append comh_hex [format %08s [format %0.2x $offset]]
    ## 
    ##   # offset for custom_hex
    ##   set offset [expr $offset + [expr [string length $boardname_hex] / 8]]
    ##   append comh_hex [format %08s [format %0.2x $offset]]
    ## 
    ##   # offset for pr custom string
    ##   set offset $pr_offset
    ##   append comh_hex [format %08s $offset]
    ## 
    ##   # pad header to match size and add checksum
    ##   set comh_hex [format %0-[expr [expr $table_size - 2] * 8]s $comh_hex]
    ##   append comh_hex "00000000" [checksum8bit $comh_hex] "000000"
    ## 
    ##   # creating file
    ##   set sys_mem_hex [format %0-[expr 512 * 8]s [concat $comh_hex$verh_hex$projname_hex$boardname_hex$custom_hex]]
    ## 
    ##   set sys_mem_file [open "mem_init_sys.txt" "w"]
    ## 
    ##   # writting 32 bits to each line
    ##   for {set i 0} {$i < [string length $sys_mem_hex]} {incr i} {
    ##     if { ($i+1) % 8 == 0} {
    ##       puts $sys_mem_file [string index $sys_mem_hex $i]
    ##     } else {
    ##       puts -nonewline $sys_mem_file [string index $sys_mem_hex $i]
    ##     }
    ##   }
    ##   close $sys_mem_file
    ## }
    ## proc sysid_gen_pr_init_file {custom_string} {
    ## 
    ##   set custom_hex [stringtohex $custom_string 64]
    ## 
    ##   # creating file
    ##   set pr_mem_file [open "mem_init_pr.txt" "w"]
    ## 
    ##   # writting 32 bits to each line
    ##   for {set i 0} {$i < [string length $custom_hex]} {incr i} {
    ##     if { ($i+1) % 8 == 0} {
    ##       puts $pr_mem_file [string index $custom_hex $i]
    ##     } else {
    ##       puts -nonewline $pr_mem_file [string index $custom_hex $i]
    ##     }
    ##   }
    ##   close $pr_mem_file
    ## }
    # adi_project daq2_zc706
    WARNING: [Device 21-436] No parts matched 'xc7z045ffg900-2'
    ERROR: [Coretcl 2-106] Specified part could not be found.
    INFO: [Common 17-206] Exiting Vivado at Tue May 14 22:14:39 2024...
    

  • WARNING: [Device 21-436] No parts matched 'xc7z045ffg900-2'
    ERROR: [Coretcl 2-106] Specified part could not be found.
    INFO: [Common 17-206] Exiting Vivado at Tue May 14 22:14:39 2024...

    Do you have a full licensed version of Vivado installed (not webpack)?

    -Travis

  • Thanks,

    1. Where are you seeing these error/warning messages?  Are they in the log file i attached?  Because I don't see them. 

    2. I do have a webpack, however, I have the zcu102 and that should have given me a license to the FPGA family on board (as that's been verified with me already doing some designs with the fpag on the zcu102), so I now changed the project to the one that's actually relevant to my board and DAC (I'm using the zcu102 with the AD9081_fmca_ebz as you probably already know from the other threads).  Anyway, now I'm getting this:  

    ****** Vivado v2019.1 (64-bit)
      **** SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
      **** IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
        ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
    
    source system_project.tcl
    # source ../../scripts/adi_env.tcl
    ## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../.."]]
    ## set ad_ghdl_dir [file normalize [file join [file dirname [info script]] "../../../ghdl"]]
    ## if [info exists ::env(ADI_HDL_DIR)] {
    ##   set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)]
    ## }
    ## if [info exists ::env(ADI_GHDL_DIR)] {
    ##   set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)]
    ## }
    ## proc get_env_param {name default_value} {
    ##   if [info exists ::env($name)] {
    ##     puts "Getting from environment the parameter: $name=$::env($name) "
    ##     return $::env($name)
    ##   } else {
    ##     return $default_value
    ##   }
    ## }
    # source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
    ## if {![info exists REQUIRED_VIVADO_VERSION]} {
    ##   set REQUIRED_VIVADO_VERSION "2019.1"
    ## }
    ## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
    ##   set IGNORE_VERSION_CHECK 1
    ## } elseif {![info exists IGNORE_VERSION_CHECK]} {
    ##   set IGNORE_VERSION_CHECK 0
    ## }
    ## if {[info exists ::env(ADI_USE_OOC_SYNTHESIS)]} {
    ##   set ADI_USE_OOC_SYNTHESIS 1
    ## } elseif {![info exists ADI_USE_OOC_SYNTHESIS]} {
    ##   set ADI_USE_OOC_SYNTHESIS 0
    ## }
    ## set ADI_USE_INCR_COMP 1
    ## set ADI_POWER_OPTIMIZATION 0
    ## set p_board "not-applicable"
    ## set p_device "none"
    ## set sys_zynq 1
    ## set p_prcfg_init ""
    ## set p_prcfg_list ""
    ## set p_prcfg_status ""
    ## proc adi_project {project_name {mode 0} {parameter_list {}} } {
    ## 
    ##   global ad_hdl_dir
    ##   global ad_ghdl_dir
    ##   global p_board
    ##   global p_device
    ##   global sys_zynq
    ##   global REQUIRED_VIVADO_VERSION
    ##   global IGNORE_VERSION_CHECK
    ##   global ADI_USE_OOC_SYNTHESIS
    ##   global ADI_USE_INCR_COMP
    ## 
    ##   if [regexp "_ac701$" $project_name] {
    ##     set p_device "xc7a200tfbg676-2"
    ##     set p_board [lindex [lsearch -all -inline [get_board_parts] *ac701*] end]
    ##     set sys_zynq 0
    ##   }
    ##   if [regexp "_kc705$" $project_name] {
    ##     set p_device "xc7k325tffg900-2"
    ##     set p_board [lindex [lsearch -all -inline [get_board_parts] *kc705*] end]
    ##     set sys_zynq 0
    ##   }
    ##   if [regexp "_vc707$" $project_name] {
    ##     set p_device "xc7vx485tffg1761-2"
    ##     set p_board [lindex [lsearch -all -inline [get_board_parts] *vc707*] end]
    ##     set sys_zynq 0
    ##   }
    ##   if [regexp "_vcu118$" $project_name] {
    ##     set p_device "xcvu9p-flga2104-2L-e"
    ##     set p_board [lindex [lsearch -all -inline [get_board_parts] *vcu118*] end]
    ##     set sys_zynq 0
    ##   }
    ##   if [regexp "_kcu105$" $project_name] {
    ##     set p_device "xcku040-ffva1156-2-e"
    ##     set p_board [lindex [lsearch -all -inline [get_board_parts] *kcu105*] end]
    ##     set sys_zynq 0
    ##   }
    ##   if [regexp "_zed$" $project_name] {
    ##     set p_device "xc7z020clg484-1"
    ##     set p_board [lindex [lsearch -all -inline [get_board_parts] *zed*] end]
    ##     set sys_zynq 1
    ##   }
    ##   if [regexp "_coraz7s$" $project_name] {
    ##     set p_device "xc7z007sclg400-1"
    ##     set p_board "not-applicable"
    ##     set sys_zynq 1
    ##   }
    ##   if [regexp "_microzed$" $project_name] {
    ##     set p_device "xc7z010clg400-1"
    ##     set p_board "not-applicable"
    ##     set sys_zynq 1
    ##   }
    ##   if [regexp "_zc702$" $project_name] {
    ##     set p_device "xc7z020clg484-1"
    ##     set p_board [lindex [lsearch -all -inline [get_board_parts] *zc702*] end]
    ##     set sys_zynq 1
    ##   }
    ##   if [regexp "_zc706$" $project_name] {
    ##     set p_device "xc7z045ffg900-2"
    ##     set p_board [lindex [lsearch -all -inline [get_board_parts] *zc706*] end]
    ##     set sys_zynq 1
    ##   }
    ##   if [regexp "_mitx045$" $project_name] {
    ##     set p_device "xc7z045ffg900-2"
    ##     set p_board "not-applicable"
    ##     set sys_zynq 1
    ##   }
    ##   if [regexp "_zcu102$" $project_name] {
    ##     set p_device "xczu9eg-ffvb1156-2-e"
    ##     set p_board [lindex [lsearch -all -inline [get_board_parts] *zcu102*] end]
    ##     set sys_zynq 2
    ##   }
    ## 
    ##   set VIVADO_VERSION [version -short]
    ##   if {$IGNORE_VERSION_CHECK} {
    ##     if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
    ##       puts -nonewline "CRITICAL WARNING: vivado version mismatch; "
    ##       puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
    ##       puts -nonewline "got $VIVADO_VERSION.\n"
    ##     }
    ##   } else {
    ##     if {[string compare $VIVADO_VERSION $REQUIRED_VIVADO_VERSION] != 0} {
    ##       puts -nonewline "ERROR: vivado version mismatch; "
    ##       puts -nonewline "expected $REQUIRED_VIVADO_VERSION, "
    ##       puts -nonewline "got $VIVADO_VERSION.\n"
    ##       puts -nonewline "This ERROR message can be down-graded to CRITICAL WARNING by setting ADI_IGNORE_VERSION_CHECK environment variable to 1. Be aware that ADI will not support you, if you are using a different tool version.\n"
    ##       exit 2
    ##     }
    ##   }
    ## 
    ##   if {$mode == 0} {
    ##     set project_system_dir "./$project_name.srcs/sources_1/bd/system"
    ##     create_project $project_name . -part $p_device -force
    ##   } else {
    ##     set project_system_dir ".srcs/sources_1/bd/system"
    ##     create_project -in_memory -part $p_device
    ##   }
    ## 
    ##   if {$mode == 1} {
    ##     file mkdir $project_name.data
    ##   }
    ## 
    ##   if {$p_board ne "not-applicable"} {
    ##     set_property board_part $p_board [current_project]
    ##   }
    ## 
    ##   set lib_dirs $ad_hdl_dir/library
    ##   if {$ad_hdl_dir ne $ad_ghdl_dir} {
    ##     lappend lib_dirs $ad_ghdl_dir/library
    ##   }
    ## 
    ##   # Set a common IP cache for all projects
    ##   if {$ADI_USE_OOC_SYNTHESIS == 1} {
    ##     if {[file exists $ad_hdl_dir/ipcache] == 0} {
    ##       file mkdir $ad_hdl_dir/ipcache
    ##     }
    ##     config_ip_cache -import_from_project -use_cache_location $ad_hdl_dir/ipcache
    ##   }
    ## 
    ##   set_property ip_repo_paths $lib_dirs [current_fileset]
    ##   update_ip_catalog
    ## 
    ##   ## Load custom message severity definitions
    ##   source $ad_hdl_dir/projects/scripts/adi_xilinx_msg.tcl
    ## 
    ##   ## In Vivado there is a limit for the number of warnings and errors which are
    ##   ## displayed by the tool for a particular error or warning; the default value
    ##   ## of this limit is 100.
    ##   ## Overrides the default limit to 2000.
    ##   set_param messaging.defaultLimit 2000
    ## 
    ##   # Set parameters of the top level file
    ##   # Make the same parameters available to system_bd.tcl
    ##   set proj_params [get_property generic [current_fileset]]
    ##   foreach {param value} $parameter_list {
    ##     lappend proj_params $param=$value
    ##     set ad_project_params($param) $value
    ##   }
    ##   set_property generic $proj_params [current_fileset]
    ## 
    ##   create_bd_design "system"
    ##   source system_bd.tcl
    ## 
    ##   save_bd_design
    ##   validate_bd_design
    ## 
    ##   if {$ADI_USE_OOC_SYNTHESIS == 1} {
    ##     set_property synth_checkpoint_mode Hierarchical [get_files  $project_system_dir/system.bd]
    ##   } else {
    ##     set_property synth_checkpoint_mode None [get_files  $project_system_dir/system.bd]
    ##   }
    ##   generate_target {synthesis implementation} [get_files  $project_system_dir/system.bd]
    ##   if {$ADI_USE_OOC_SYNTHESIS == 1} {
    ##     export_ip_user_files -of_objects [get_files  $project_system_dir/system.bd] -no_script -sync -force -quiet
    ##     create_ip_run [get_files  $project_system_dir/system.bd]
    ##   }
    ##   make_wrapper -files [get_files $project_system_dir/system.bd] -top
    ## 
    ##   if {$mode == 0} {
    ##     import_files -force -norecurse -fileset sources_1 $project_system_dir/hdl/system_wrapper.v
    ##   } else {
    ##     write_hwdef -file "$project_name.data/$project_name.hwdef"
    ##   }
    ## 
    ##   if {$ADI_USE_INCR_COMP == 1} {
    ##     if {[file exists ./reference.dcp]} {
    ##       set_property incremental_checkpoint ./reference.dcp [get_runs impl_1]
    ##     }
    ##   }
    ## 
    ## }
    ## proc adi_project_files {project_name project_files} {
    ## 
    ##   foreach pfile $project_files {
    ##     if {[string range $pfile [expr 1 + [string last . $pfile]] end] == "xdc"} {
    ##       add_files -norecurse -fileset constrs_1 $pfile
    ##     } else {
    ##       add_files -norecurse -fileset sources_1 $pfile
    ##     }
    ##   }
    ## 
    ##   # NOTE: top file name is always system_top
    ##   set_property top system_top [current_fileset]
    ## }
    ## proc adi_project_run {project_name} {
    ## 
    ##   global ADI_POWER_OPTIMIZATION
    ##   global ADI_USE_OOC_SYNTHESIS
    ## 
    ##   if {$ADI_USE_OOC_SYNTHESIS == 1} {
    ##     launch_runs -jobs 4 system_*_synth_1 synth_1
    ##   } else {
    ##     launch_runs synth_1
    ##   }
    ##   wait_on_run synth_1
    ##   open_run synth_1
    ##   report_timing_summary -file timing_synth.log
    ## 
    ##   if {![info exists ::env(ADI_NO_BITSTREAM_COMPRESSION)] && ![info exists ADI_NO_BITSTREAM_COMPRESSION]} {
    ##     set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
    ##   }
    ## 
    ##   if {$ADI_POWER_OPTIMIZATION == 1} {
    ##   set_property STEPS.POWER_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
    ##   set_property STEPS.POST_PLACE_POWER_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
    ##   }
    ## 
    ##   launch_runs impl_1 -to_step write_bitstream
    ##   wait_on_run impl_1
    ##   open_run impl_1
    ##   report_timing_summary -warn_on_violation -file timing_impl.log
    ## 
    ##   if {[info exists ::env(ADI_GENERATE_UTILIZATION)]} {
    ##     set csv_file resource_utilization.csv
    ##     if {[ catch {
    ##       xilinx::designutils::report_failfast -csv -file $csv_file -transpose -no_header -ignore_pr -quiet
    ##       set MMCM [llength [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ *MMCM* }]]
    ##       set PLL [llength [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ *PLL* }]]
    ##       set worst_slack_setup [get_property SLACK [get_timing_paths -setup]]
    ##       set worst_slack_hold [get_property SLACK [get_timing_paths -hold]]
    ## 
    ##       set fileRead [open $csv_file r]
    ##       set lines [split [read $fileRead] "\n"]
    ##       set names_line [lindex $lines end-3]
    ##       set values_line [lindex $lines end-2]
    ##       close $fileRead
    ## 
    ##       set fileWrite [open $csv_file w]
    ##       puts $fileWrite "$names_line,MMCM*,PLL*,Worst_Setup_Slack,Worst_Hold_Slack"
    ##       puts $fileWrite "$values_line,$MMCM,$PLL,$worst_slack_setup,$worst_slack_hold"
    ##       close $fileWrite
    ##       } issue ] != 0 } {
    ##         puts "GENERATE_REPORTS: tclapp::xilinx::designutils not installed"
    ##       }
    ## 
    ##       # Define a list of IPs for which to generate report utilization
    ##       set IP_list {
    ##         ad_ip_jesd_204_tpl_adc
    ##         ad_ip_jesd_204_tpl_dac
    ##         axi_jesd204_rx
    ##         axi_jesd204_tx
    ##         jesd204_rx
    ##         jesd204_tx
    ##         axi_adxcvr
    ##         util_adxcvr
    ##         axi_dmac
    ##         util_cpack2
    ##         util_upack2
    ##       }
    ## 
    ##       foreach IP_name $IP_list {
    ## 	set output_file ${IP_name}_resource_utilization.log
    ##         file delete $output_file
    ##         foreach IP_instance [ get_cells -quiet -hierarchical -filter " ORIG_REF_NAME =~ $IP_name || REF_NAME =~ $IP_name " ] {
    ##           report_utilization -hierarchical -hierarchical_depth 1 -cells $IP_instance -file $output_file -append -quiet
    ##           report_property $IP_instance -file $output_file -append -quiet
    ##           set report_file [ open $output_file a ]
    ##           puts $report_file "\n\n\n"
    ##           close $report_file
    ##         }
    ##       }
    ##     } else {
    ##     puts "GENERATE_REPORTS: Resource utilization files won't be generated because ADI_GENERATE_UTILIZATION env var is not set"
    ##   }
    ## 
    ##   if {[info exists ::env(ADI_GENERATE_XPA)]} {
    ##     set csv_file power_analysis.csv
    ##     set Layers "8to11"
    ##     set CapLoad "20"
    ##     set ToggleRate "15.00000"
    ##     set StatProb "0.500000"
    ## 
    ##     set_load $CapLoad [all_outputs]
    ##     set_operating_conditions -board_layers $Layers
    ##     set_switching_activity -default_toggle_rate $ToggleRate
    ##     set_switching_activity -default_static_probability $StatProb
    ##     set_switching_activity -type lut -toggle_rate $ToggleRate -static_probability $StatProb -all
    ##     set_switching_activity -type register -toggle_rate $ToggleRate -static_probability $StatProb -all
    ##     set_switching_activity -type shift_register -toggle_rate $ToggleRate -static_probability $StatProb -all
    ##     set_switching_activity -type lut_ram -toggle_rate $ToggleRate -static_probability $StatProb -all
    ##     set_switching_activity -type bram -toggle_rate $ToggleRate -static_probability $StatProb -all
    ##     set_switching_activity -type dsp -toggle_rate $ToggleRate -static_probability $StatProb -all
    ##     set_switching_activity -type gt_rxdata -toggle_rate $ToggleRate -static_probability $StatProb -all
    ##     set_switching_activity -type gt_txdata -toggle_rate $ToggleRate -static_probability $StatProb -all
    ##     set_switching_activity -type io_output -toggle_rate $ToggleRate -static_probability $StatProb -all
    ##     set_switching_activity -type bram_enable -toggle_rate $ToggleRate -static_probability $StatProb -all
    ##     set_switching_activity -type bram_wr_enable -toggle_rate $ToggleRate -static_probability $StatProb -all
    ##     set_switching_activity -type io_bidir_enable -toggle_rate $ToggleRate -static_probability $StatProb -all
    ##     report_power -file $csv_file
    ## 
    ##     set fileRead [open $csv_file r]
    ##     set filecontent [read $fileRead]
    ##     set input_list [split $filecontent "\n"]
    ## 
    ##     set TextList [lsearch -all -inline $input_list "*Total On-Chip Power (W)*"]
    ##     set on_chip_pwr "[lindex [lindex $TextList 0] 6] W"
    ##     set TextList [lsearch -all -inline $input_list "*Junction Temperature (C)*"]
    ##     set junction_temp "[lindex [lindex $TextList 0] 5] *C"
    ##     close $fileRead
    ## 
    ##     set fileWrite [open $csv_file w]
    ##     puts $fileWrite "On-chip_power,Junction_temp"
    ##     puts $fileWrite "$on_chip_pwr,$junction_temp"
    ##     close $fileWrite
    ##   } else {
    ##     puts "GENERATE_REPORTS: Power analysis files won't be generated because ADI_GENERATE_XPA env var is not set"
    ##   }
    ## 
    ##   # Look for undefined clocks which do not show up in the timing summary
    ##   set timing_check [check_timing -override_defaults no_clock -no_header -return_string]
    ##   if {[regexp { (\d+) register} $timing_check -> num_regs]} {
    ## 
    ##     if {[info exist num_regs]} {
    ##       if {$num_regs > 0} {
    ##         puts "CRITICAL WARNING: There are $num_regs registers with no clocks !!! See no_clock.log for details."
    ##         check_timing -override_defaults no_clock -verbose -file no_clock.log
    ##       }
    ##     }
    ## 
    ##   } else {
    ##     puts "CRITICAL WARNING: The search for undefined clocks failed !!!"
    ##   }
    ## 
    ##   file mkdir $project_name.sdk
    ## 
    ##   set timing_string $[report_timing_summary -return_string]
    ##   if { [string match "*VIOLATED*" $timing_string] == 1 ||
    ##        [string match "*Timing constraints are not met*" $timing_string] == 1} {
    ##     file copy -force $project_name.runs/impl_1/system_top.sysdef $project_name.sdk/system_top_bad_timing.hdf
    ##     return -code error [format "ERROR: Timing Constraints NOT met!"]
    ##   } else {
    ##     file copy -force $project_name.runs/impl_1/system_top.sysdef $project_name.sdk/system_top.hdf
    ##   }
    ## }
    ## proc adi_project_synth {project_name prcfg_name hdl_files {xdc_files ""}} {
    ## 
    ##   global p_device
    ## 
    ##   set p_prefix "$project_name.data/$project_name"
    ## 
    ##   if {$prcfg_name eq ""} {
    ## 
    ##     read_verilog .srcs/sources_1/bd/system/hdl/system_wrapper.v
    ##     read_verilog $hdl_files
    ##     read_xdc $xdc_files
    ## 
    ##     synth_design -mode default -top system_top -part $p_device > $p_prefix.synth.rds
    ##     write_checkpoint -force $p_prefix.synth.dcp
    ##     close_project
    ## 
    ##   } else {
    ## 
    ##     create_project -in_memory -part $p_device
    ##     read_verilog $hdl_files
    ##     synth_design -mode out_of_context -top "prcfg" -part $p_device > $p_prefix.${prcfg_name}_synth.rds
    ##     write_checkpoint -force $p_prefix.${prcfg_name}_synth.dcp
    ##     close_project
    ##   }
    ## }
    ## proc adi_project_impl {project_name prcfg_name {xdc_files ""}} {
    ## 
    ##   global p_device
    ##   global p_prcfg_init
    ##   global p_prcfg_list
    ##   global p_prcfg_status
    ## 
    ##   set p_prefix "$project_name.data/$project_name"
    ## 
    ##   if {$prcfg_name eq "default"} {
    ##     set p_prcfg_status 0
    ##     set p_prcfg_list ""
    ##     set p_prcfg_init "$p_prefix.${prcfg_name}_impl.dcp"
    ##     file mkdir $project_name.sdk
    ##   }
    ## 
    ##   if {$prcfg_name eq "default"} {
    ## 
    ##     open_checkpoint $p_prefix.synth.dcp -part $p_device
    ##     read_xdc $xdc_files
    ##     read_checkpoint -cell i_prcfg $p_prefix.${prcfg_name}_synth.dcp
    ##     set_property HD.RECONFIGURABLE 1 [get_cells i_prcfg]
    ##     opt_design > $p_prefix.${prcfg_name}_opt.rds
    ##     write_debug_probes -force $p_prefix.${prcfg_name}_debug_nets.ltx
    ##     place_design > $p_prefix.${prcfg_name}_place.rds
    ##     route_design > $p_prefix.${prcfg_name}_route.rds
    ## 
    ##   } else {
    ## 
    ##     open_checkpoint $p_prefix.default_impl_bb.dcp -part $p_device
    ##     lock_design -level routing
    ##     read_checkpoint -cell i_prcfg $p_prefix.${prcfg_name}_synth.dcp
    ##     read_xdc $xdc_files
    ##     opt_design > $p_prefix.${prcfg_name}_opt.rds
    ##     place_design > $p_prefix.${prcfg_name}_place.rds
    ##     route_design > $p_prefix.${prcfg_name}_route.rds
    ##   }
    ## 
    ##   write_checkpoint -force $p_prefix.${prcfg_name}_impl.dcp
    ##   report_utilization -pblocks pb_prcfg -file $p_prefix.${prcfg_name}_utilization.rpt
    ##   report_timing_summary -file $p_prefix.${prcfg_name}_timing_summary.rpt
    ## 
    ##   if [expr [get_property SLACK [get_timing_paths]] < 0] {
    ##     set p_prcfg_status 1
    ##     puts "CRITICAL WARNING: Timing Constraints NOT met ($prcfg_name)!"
    ##   }
    ## 
    ##   write_checkpoint -force -cell i_prcfg $p_prefix.${prcfg_name}_prcfg_impl.dcp
    ##   update_design -cell i_prcfg -black_box
    ##   write_checkpoint -force $p_prefix.${prcfg_name}_impl_bb.dcp
    ##   open_checkpoint $p_prefix.${prcfg_name}_impl.dcp -part $p_device
    ##   write_bitstream -force -bin_file -file $p_prefix.${prcfg_name}.bit
    ##   write_sysdef -hwdef $p_prefix.hwdef -bitfile $p_prefix.${prcfg_name}.bit -file $p_prefix.${prcfg_name}.hdf
    ##   file copy -force $p_prefix.${prcfg_name}.hdf $project_name.sdk/system_top.${prcfg_name}.hdf
    ## 
    ##   if {$prcfg_name ne "default"} {
    ##     lappend p_prcfg_list "$p_prefix.${prcfg_name}_impl.dcp"
    ##   }
    ## 
    ##   if {$prcfg_name eq "default"} {
    ##     file copy -force $p_prefix.${prcfg_name}.hdf $project_name.sdk/system_top.hdf
    ##   }
    ## }
    ## proc adi_project_verify {project_name} {
    ## 
    ##   # checkpoint for the default design
    ##   global p_prcfg_init
    ##   # list of checkpoints with all the PRs integrated into the default design
    ##   global p_prcfg_list
    ##   global p_prcfg_status
    ## 
    ##   set p_prefix "$project_name.data/$project_name"
    ## 
    ##   pr_verify -full_check -initial $p_prcfg_init \
    ##     -additional $p_prcfg_list \
    ##     -file $p_prefix.prcfg_verify.log
    ## 
    ##   if {$p_prcfg_status == 1} {
    ##     return -code error [format "ERROR: Timing Constraints NOT met!"]
    ##   }
    ## }
    # source $ad_hdl_dir/projects/scripts/adi_board.tcl
    ## set sys_cpu_interconnect_index 0
    ## set sys_hp0_interconnect_index -1
    ## set sys_hp1_interconnect_index -1
    ## set sys_hp2_interconnect_index -1
    ## set sys_hp3_interconnect_index -1
    ## set sys_mem_interconnect_index -1
    ## set sys_mem_clk_index 0
    ## set xcvr_index -1
    ## set xcvr_tx_index 0
    ## set xcvr_rx_index 0
    ## set xcvr_instance NONE
    ## proc ad_ip_instance {i_ip i_name {i_params {}}} {
    ## 
    ##   set cell [create_bd_cell -type ip -vlnv [get_ipdefs -all -filter "VLNV =~ *:${i_ip}:* && \
    ##     design_tool_contexts =~ *IPI* && UPGRADE_VERSIONS == \"\""] ${i_name}]
    ##   if {$i_params != {}} {
    ##     set config {}
    ##     # Add CONFIG. prefix to all config options
    ##     foreach {k v} $i_params {
    ##       lappend config "CONFIG.$k" $v
    ##     }
    ##     set_property -dict $config $cell
    ##   }
    ## }
    ## proc ad_ip_parameter {i_name i_param i_value} {
    ## 
    ##   set_property ${i_param} ${i_value} [get_bd_cells ${i_name}]
    ## }
    ## proc ad_connect_type {p_name} {
    ## 
    ##   set m_name ""
    ## 
    ##   if {$m_name eq ""} {set m_name [get_bd_intf_pins  -quiet $p_name]}
    ##   if {$m_name eq ""} {set m_name [get_bd_pins       -quiet $p_name]}
    ##   if {$m_name eq ""} {set m_name [get_bd_intf_ports -quiet $p_name]}
    ##   if {$m_name eq ""} {set m_name [get_bd_ports      -quiet $p_name]}
    ##   if {$m_name eq ""} {set m_name [get_bd_intf_nets  -quiet $p_name]}
    ##   if {$m_name eq ""} {set m_name [get_bd_nets       -quiet $p_name]}
    ## 
    ##   return $m_name
    ## }
    ## proc ad_connect {p_name_1 p_name_2} {
    ## 
    ##   ## connect an IPI object to GND or VCC
    ##   ## instantiate xlconstant with the required width module if there isn't any
    ##   ## already
    ##   if {($p_name_2 eq "GND") || ($p_name_2 eq "VCC")} {
    ##     set p_size 1
    ##     set p_msb [get_property left [get_bd_pins $p_name_1]]
    ##     set p_lsb [get_property right [get_bd_pins $p_name_1]]
    ##     if {($p_msb ne "") && ($p_lsb ne "")} {
    ##       set p_size [expr (($p_msb + 1) - $p_lsb)]
    ##     }
    ##     set p_cell_name "$p_name_2\_$p_size"
    ##     if {[get_bd_cells -quiet $p_cell_name] eq ""} {
    ##       if {$p_name_2 eq "VCC"} {
    ##         set p_value [expr (1 << $p_size) - 1]
    ##       } else {
    ##         set p_value 0
    ##       }
    ##       ad_ip_instance xlconstant $p_cell_name
    ##       set_property CONFIG.CONST_WIDTH $p_size [get_bd_cells $p_cell_name]
    ##       set_property CONFIG.CONST_VAL $p_value [get_bd_cells $p_cell_name]
    ##     }
    ##     puts "connect_bd_net $p_cell_name/dout $p_name_1"
    ##     connect_bd_net [get_bd_pins $p_name_1] [get_bd_pins $p_cell_name/dout]
    ##     return
    ##   }
    ## 
    ##   set m_name_1 [ad_connect_type $p_name_1]
    ##   set m_name_2 [ad_connect_type $p_name_2]
    ## 
    ##   if {$m_name_1 eq ""} {
    ##     if {[get_property CLASS $m_name_2] eq "bd_intf_pin"} {
    ##       puts "create_bd_intf_net $p_name_1"
    ##       create_bd_intf_net $p_name_1
    ##     }
    ##     if {[get_property CLASS $m_name_2] eq "bd_pin"} {
    ##       puts "create_bd_net $p_name_1"
    ##       create_bd_net $p_name_1
    ##     }
    ##     set m_name_1 [ad_connect_type $p_name_1]
    ##   }
    ## 
    ##   if {[get_property CLASS $m_name_1] eq "bd_intf_pin"} {
    ##     puts "connect_bd_intf_net $m_name_1 $m_name_2"
    ##     connect_bd_intf_net $m_name_1 $m_name_2
    ##     return
    ##   }
    ## 
    ##   if {[get_property CLASS $m_name_1] eq "bd_pin"} {
    ##     puts "connect_bd_net $m_name_1 $m_name_2"
    ##     connect_bd_net $m_name_1 $m_name_2
    ##     return
    ##   }
    ## 
    ##   if {[get_property CLASS $m_name_1] eq "bd_net"} {
    ##     puts "connect_bd_net -net $m_name_1 $m_name_2"
    ##     connect_bd_net -net $m_name_1 $m_name_2
    ##     return
    ##   }
    ## }
    ## proc ad_disconnect {p_name_1 p_name_2} {
    ## 
    ##   set m_name_1 [ad_connect_type $p_name_1]
    ##   set m_name_2 [ad_connect_type $p_name_2]
    ## 
    ##   if {[get_property CLASS $m_name_1] eq "bd_net"} {
    ##     disconnect_bd_net $m_name_1 $m_name_2
    ##     return
    ##   }
    ## 
    ##   if {[get_property CLASS $m_name_1] eq "bd_port"} {
    ##     delete_bd_objs -quiet [get_bd_nets -quiet -of_objects \
    ##       [find_bd_objs -relation connected_to $m_name_1]]
    ##     delete_bd_objs -quiet $m_name_1
    ##     return
    ##   }
    ## 
    ##   if {[get_property CLASS $m_name_1] eq "bd_pin"} {
    ##     delete_bd_objs -quiet [get_bd_nets -quiet -of_objects \
    ##       [find_bd_objs -relation connected_to $m_name_1]]
    ##     delete_bd_objs -quiet $m_name_1
    ##     return
    ##   }
    ## }
    ## proc ad_xcvrcon {u_xcvr a_xcvr a_jesd {lane_map {}} {device_clk {}}} {
    ## 
    ##   global xcvr_index
    ##   global xcvr_tx_index
    ##   global xcvr_rx_index
    ##   global xcvr_instance
    ## 
    ##   set no_of_lanes [get_property CONFIG.NUM_OF_LANES [get_bd_cells $a_xcvr]]
    ##   set qpll_enable [get_property CONFIG.QPLL_ENABLE [get_bd_cells $a_xcvr]]
    ##   set tx_or_rx_n [get_property CONFIG.TX_OR_RX_N [get_bd_cells $a_xcvr]]
    ## 
    ##   set jesd204_bd_type [get_property TYPE [get_bd_cells $a_jesd]]
    ## 
    ##   if {$jesd204_bd_type == "hier"} {
    ##     set jesd204_type 0
    ##   } else {
    ##     set jesd204_type 1
    ##   }
    ## 
    ##   if {$xcvr_instance ne $u_xcvr} {
    ##     set xcvr_index [expr ($xcvr_index + 1)]
    ##     set xcvr_tx_index 0
    ##     set xcvr_rx_index 0
    ##     set xcvr_instance $u_xcvr
    ##   }
    ## 
    ##   set txrx "rx"
    ##   set data_dir "I"
    ##   set ctrl_dir "O"
    ##   set index $xcvr_rx_index
    ## 
    ##   if {$tx_or_rx_n == 1} {
    ## 
    ##     set txrx "tx"
    ##     set data_dir "O"
    ##     set ctrl_dir "I"
    ##     set index $xcvr_tx_index
    ##   }
    ## 
    ##   set m_sysref ${txrx}_sysref_${index}
    ##   set m_sync ${txrx}_sync_${index}
    ##   set m_data ${txrx}_data
    ## 
    ##   if {$xcvr_index >= 1} {
    ## 
    ##     set m_sysref ${txrx}_sysref_${xcvr_index}_${index}
    ##     set m_sync ${txrx}_sync_${xcvr_index}_${index}
    ##     set m_data ${txrx}_data_${xcvr_index}
    ##   }
    ## 
    ##   if {$jesd204_type == 0} {
    ##     set num_of_links [get_property CONFIG.NUM_LINKS [get_bd_cells $a_jesd/$txrx]]
    ##   } else {
    ##     set num_of_links 1
    ##   }
    ## 
    ##   create_bd_port -dir I $m_sysref
    ##   create_bd_port -from [expr $num_of_links - 1] -to 0 -dir ${ctrl_dir} $m_sync
    ## 
    ##   if {$device_clk == {}} {
    ##     set device_clk ${u_xcvr}/${txrx}_out_clk_${index}
    ##     set rst_gen [regsub -all "/" ${a_jesd}_rstgen "_"]
    ##     set create_rst_gen 1
    ##   } else {
    ##     set rst_gen ${device_clk}_rstgen
    ##     # Only create one reset gen per clock
    ##     set create_rst_gen [expr {[get_bd_cells -quiet ${rst_gen}] == {}}]
    ##   }
    ## 
    ##   if {${create_rst_gen}} {
    ##     ad_ip_instance proc_sys_reset ${rst_gen}
    ##     ad_connect ${device_clk} ${rst_gen}/slowest_sync_clk
    ##     ad_connect sys_cpu_resetn ${rst_gen}/ext_reset_in
    ##   }
    ## 
    ##   for {set n 0} {$n < $no_of_lanes} {incr n} {
    ## 
    ##     set m [expr ($n + $index)]
    ## 
    ## 
    ##     if {$lane_map != {}} {
    ##       set phys_lane [lindex $lane_map $n]
    ##     } else {
    ##       set phys_lane $m
    ##     }
    ## 
    ##     if {$tx_or_rx_n == 0} {
    ##       ad_connect  ${a_xcvr}/up_es_${n} ${u_xcvr}/up_es_${phys_lane}
    ##       if {$jesd204_type == 0} {
    ##         ad_connect  ${a_jesd}/phy_en_char_align ${u_xcvr}/${txrx}_calign_${phys_lane}
    ##       } else {
    ##         ad_connect  ${a_jesd}/rxencommaalign_out ${u_xcvr}/${txrx}_calign_${phys_lane}
    ##       }
    ##     }
    ## 
    ##     if {(($n%4) == 0) && ($qpll_enable == 1)} {
    ##       ad_connect  ${a_xcvr}/up_cm_${n} ${u_xcvr}/up_cm_${n}
    ##     }
    ##     ad_connect  ${a_xcvr}/up_ch_${n} ${u_xcvr}/up_${txrx}_${phys_lane}
    ##     ad_connect  ${device_clk} ${u_xcvr}/${txrx}_clk_${phys_lane}
    ##     if {$phys_lane != {}} {
    ##       if {$jesd204_type == 0} {
    ##         ad_connect  ${u_xcvr}/${txrx}_${phys_lane} ${a_jesd}/${txrx}_phy${n}
    ##       } else {
    ##         ad_connect  ${u_xcvr}/${txrx}_${phys_lane} ${a_jesd}/gt${n}_${txrx}
    ##       }
    ##     }
    ## 
    ##     create_bd_port -dir ${data_dir} ${m_data}_${m}_p
    ##     create_bd_port -dir ${data_dir} ${m_data}_${m}_n
    ##     ad_connect  ${u_xcvr}/${txrx}_${m}_p ${m_data}_${m}_p
    ##     ad_connect  ${u_xcvr}/${txrx}_${m}_n ${m_data}_${m}_n
    ##   }
    ## 
    ##   if {$jesd204_type == 0} {
    ##     ad_connect  ${a_jesd}/sysref $m_sysref
    ##     ad_connect  ${a_jesd}/sync $m_sync
    ##     ad_connect  ${device_clk} ${a_jesd}/device_clk
    ##   } else {
    ##     ad_connect  ${a_jesd}/${txrx}_sysref $m_sysref
    ##     ad_connect  ${a_jesd}/${txrx}_sync $m_sync
    ##     ad_connect  ${device_clk} ${a_jesd}/${txrx}_core_clk
    ##     ad_connect  ${a_xcvr}/up_status ${a_jesd}/${txrx}_reset_done
    ##     ad_connect  ${rst_gen}/peripheral_reset ${a_jesd}/${txrx}_reset
    ##   }
    ## 
    ##   if {$tx_or_rx_n == 0} {
    ##     set xcvr_rx_index [expr ($xcvr_rx_index + $no_of_lanes)]
    ##   }
    ## 
    ##   if {$tx_or_rx_n == 1} {
    ##     set xcvr_tx_index [expr ($xcvr_tx_index + $no_of_lanes)]
    ##   }
    ## }
    ## proc ad_xcvrpll {m_src m_dst} {
    ## 
    ##   foreach p_dst [get_bd_pins -quiet $m_dst] {
    ##     connect_bd_net [ad_connect_type $m_src] $p_dst
    ##   }
    ## }
    ## proc ad_mem_hp0_interconnect {p_clk p_name} {
    ## 
    ##   global sys_zynq
    ## 
    ##   if {($sys_zynq == 0) && ($p_name eq "sys_ps7/S_AXI_HP0")} {return}
    ##   if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
    ##   if {$sys_zynq >= 1} {ad_mem_hpx_interconnect "HP0" $p_clk $p_name}
    ## }
    ## proc ad_mem_hp1_interconnect {p_clk p_name} {
    ## 
    ##   global sys_zynq
    ## 
    ##   if {($sys_zynq == 0) && ($p_name eq "sys_ps7/S_AXI_HP1")} {return}
    ##   if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
    ##   if {$sys_zynq >= 1} {ad_mem_hpx_interconnect "HP1" $p_clk $p_name}
    ## }
    ## proc ad_mem_hp2_interconnect {p_clk p_name} {
    ## 
    ##   global sys_zynq
    ## 
    ##   if {($sys_zynq == 0) && ($p_name eq "sys_ps7/S_AXI_HP2")} {return}
    ##   if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
    ##   if {$sys_zynq >= 1} {ad_mem_hpx_interconnect "HP2" $p_clk $p_name}
    ## }
    ## proc ad_mem_hp3_interconnect {p_clk p_name} {
    ## 
    ##   global sys_zynq
    ## 
    ##   if {($sys_zynq == 0) && ($p_name eq "sys_ps7/S_AXI_HP3")} {return}
    ##   if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
    ##   if {$sys_zynq >= 1} {ad_mem_hpx_interconnect "HP3" $p_clk $p_name}
    ## }
    ## proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
    ## 
    ##   global sys_zynq
    ##   global sys_ddr_addr_seg
    ##   global sys_hp0_interconnect_index
    ##   global sys_hp1_interconnect_index
    ##   global sys_hp2_interconnect_index
    ##   global sys_hp3_interconnect_index
    ##   global sys_mem_interconnect_index
    ##   global sys_mem_clk_index
    ## 
    ##   set p_name_int $p_name
    ##   set p_clk_source [get_bd_pins -filter {DIR == O} -of_objects [get_bd_nets $p_clk]]
    ## 
    ##   if {$p_sel eq "MEM"} {
    ##     if {$sys_mem_interconnect_index < 0} {
    ##       ad_ip_instance smartconnect axi_mem_interconnect
    ##     }
    ##     set m_interconnect_index $sys_mem_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_mem_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs -of_objects [get_bd_cells axi_ddr_cntrl]]
    ##   }
    ## 
    ##   if {($p_sel eq "HP0") && ($sys_zynq == 1)} {
    ##     if {$sys_hp0_interconnect_index < 0} {
    ##       set p_name_int sys_ps7/S_AXI_HP0
    ##       set_property CONFIG.PCW_USE_S_AXI_HP0 {1} [get_bd_cells sys_ps7]
    ##       ad_ip_instance smartconnect axi_hp0_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hp0_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hp0_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP0/HP0_DDR_LOWOCM]
    ##   }
    ## 
    ##   if {($p_sel eq "HP1") && ($sys_zynq == 1)} {
    ##     if {$sys_hp1_interconnect_index < 0} {
    ##       set p_name_int sys_ps7/S_AXI_HP1
    ##       set_property CONFIG.PCW_USE_S_AXI_HP1 {1} [get_bd_cells sys_ps7]
    ##       ad_ip_instance smartconnect axi_hp1_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hp1_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hp1_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM]
    ##   }
    ## 
    ##   if {($p_sel eq "HP2") && ($sys_zynq == 1)} {
    ##     if {$sys_hp2_interconnect_index < 0} {
    ##       set p_name_int sys_ps7/S_AXI_HP2
    ##       set_property CONFIG.PCW_USE_S_AXI_HP2 {1} [get_bd_cells sys_ps7]
    ##       ad_ip_instance smartconnect axi_hp2_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hp2_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hp2_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM]
    ##   }
    ## 
    ##   if {($p_sel eq "HP3") && ($sys_zynq == 1)} {
    ##     if {$sys_hp3_interconnect_index < 0} {
    ##       set p_name_int sys_ps7/S_AXI_HP3
    ##       set_property CONFIG.PCW_USE_S_AXI_HP3 {1} [get_bd_cells sys_ps7]
    ##       ad_ip_instance smartconnect axi_hp3_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hp3_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hp3_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM]
    ##   }
    ## 
    ##   if {($p_sel eq "HP0") && ($sys_zynq == 2)} {
    ##     if {$sys_hp0_interconnect_index < 0} {
    ##       set p_name_int sys_ps8/S_AXI_HP0_FPD
    ##       set_property CONFIG.PSU__USE__S_AXI_GP2 {1} [get_bd_cells sys_ps8]
    ##       ad_ip_instance smartconnect axi_hp0_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hp0_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hp0_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps8/SAXIGP2/HP0_DDR_*]
    ##   }
    ## 
    ##   if {($p_sel eq "HP1") && ($sys_zynq == 2)} {
    ##     if {$sys_hp1_interconnect_index < 0} {
    ##       set p_name_int sys_ps8/S_AXI_HP1_FPD
    ##       set_property CONFIG.PSU__USE__S_AXI_GP3 {1} [get_bd_cells sys_ps8]
    ##       ad_ip_instance smartconnect axi_hp1_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hp1_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hp1_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps8/SAXIGP3/HP1_DDR_*]
    ##   }
    ## 
    ##   if {($p_sel eq "HP2") && ($sys_zynq == 2)} {
    ##     if {$sys_hp2_interconnect_index < 0} {
    ##       set p_name_int sys_ps8/S_AXI_HP2_FPD
    ##       set_property CONFIG.PSU__USE__S_AXI_GP4 {1} [get_bd_cells sys_ps8]
    ##       ad_ip_instance smartconnect axi_hp2_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hp2_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hp2_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps8/SAXIGP4/HP2_DDR_*]
    ##   }
    ## 
    ##   if {($p_sel eq "HP3") && ($sys_zynq == 2)} {
    ##     if {$sys_hp3_interconnect_index < 0} {
    ##       set p_name_int sys_ps8/S_AXI_HP3_FPD
    ##       set_property CONFIG.PSU__USE__S_AXI_GP5 {1} [get_bd_cells sys_ps8]
    ##       ad_ip_instance smartconnect axi_hp3_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hp3_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hp3_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps8/SAXIGP5/HP3_DDR_*]
    ##   }
    ## 
    ##   set i_str "S$m_interconnect_index"
    ##   if {$m_interconnect_index < 10} {
    ##     set i_str "S0$m_interconnect_index"
    ##   }
    ## 
    ##   set m_interconnect_index [expr $m_interconnect_index + 1]
    ## 
    ##   set p_intf_name [lrange [split $p_name_int "/"] end end]
    ##   set p_cell_name [lrange [split $p_name_int "/"] 0 0]
    ##   set p_intf_clock [get_bd_pins -filter "TYPE == clk && (CONFIG.ASSOCIATED_BUSIF == ${p_intf_name} || \
    ##     CONFIG.ASSOCIATED_BUSIF =~ ${p_intf_name}:* || CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name} || \
    ##     CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name}:*)" -quiet -of_objects [get_bd_cells $p_cell_name]]
    ##   if {[find_bd_objs -quiet -relation connected_to $p_intf_clock] ne "" ||
    ##       $p_intf_clock eq $p_clk_source} {
    ##     set p_intf_clock ""
    ##   }
    ## 
    ##   regsub clk $p_clk resetn p_rst
    ##   if {[get_bd_nets -quiet $p_rst] eq ""} {
    ##     set p_rst sys_cpu_resetn
    ##   }
    ## 
    ##   if {$m_interconnect_index == 0} {
    ##     set_property CONFIG.NUM_MI 1 $m_interconnect_cell
    ##     set_property CONFIG.NUM_SI 1 $m_interconnect_cell
    ##     ad_connect $p_rst $m_interconnect_cell/ARESETN
    ##     ad_connect $p_clk $m_interconnect_cell/ACLK
    ##     ad_connect $m_interconnect_cell/M00_AXI $p_name_int
    ##     if {$p_intf_clock ne ""} {
    ##       ad_connect $p_clk $p_intf_clock
    ##     }
    ##   } else {
    ## 
    ##     set_property CONFIG.NUM_SI $m_interconnect_index $m_interconnect_cell
    ##     if {[lsearch [get_bd_nets -of_object [get_bd_pins $m_interconnect_cell/ACLK*]] [get_bd_nets $p_clk]] == -1 } {
    ##         incr sys_mem_clk_index
    ##         set_property CONFIG.NUM_CLKS [expr $sys_mem_clk_index +1] $m_interconnect_cell
    ##         ad_connect $p_clk $m_interconnect_cell/ACLK$sys_mem_clk_index
    ##     }
    ##     ad_connect $m_interconnect_cell/${i_str}_AXI $p_name_int
    ##     if {$p_intf_clock ne ""} {
    ##       ad_connect $p_clk $p_intf_clock
    ##     }
    ## 
    ##     set mem_mapped [get_bd_addr_segs -of [get_bd_addr_spaces -of  [get_bd_intf_pins -filter {NAME=~ *DLMB*} -of [get_bd_cells /sys_mb]]] -filter {NAME=~ *DDR* || NAME=~ *ddr*}]
    ## 
    ##     if {$mem_mapped eq ""} {
    ##       assign_bd_address $m_addr_seg
    ##     } else {
    ##       assign_bd_address -offset [get_property OFFSET $mem_mapped] \
    ##                         -range  [get_property RANGE $mem_mapped] $m_addr_seg
    ##     }
    ##   }
    ## 
    ##   if {$p_sel eq "MEM"} {set sys_mem_interconnect_index $m_interconnect_index}
    ##   if {$p_sel eq "HP0"} {set sys_hp0_interconnect_index $m_interconnect_index}
    ##   if {$p_sel eq "HP1"} {set sys_hp1_interconnect_index $m_interconnect_index}
    ##   if {$p_sel eq "HP2"} {set sys_hp2_interconnect_index $m_interconnect_index}
    ##   if {$p_sel eq "HP3"} {set sys_hp3_interconnect_index $m_interconnect_index}
    ## 
    ## }
    ## proc ad_cpu_interconnect {p_address p_name} {
    ## 
    ##   global sys_zynq
    ##   global sys_cpu_interconnect_index
    ## 
    ##   set i_str "M$sys_cpu_interconnect_index"
    ##   if {$sys_cpu_interconnect_index < 10} {
    ##     set i_str "M0$sys_cpu_interconnect_index"
    ##   }
    ## 
    ##   if {$sys_cpu_interconnect_index == 0} {
    ##     ad_ip_instance axi_interconnect axi_cpu_interconnect
    ##     if {$sys_zynq == 2} {
    ##       ad_connect sys_cpu_clk sys_ps8/maxihpm0_lpd_aclk
    ##       ad_connect sys_cpu_clk axi_cpu_interconnect/ACLK
    ##       ad_connect sys_cpu_clk axi_cpu_interconnect/S00_ACLK
    ##       ad_connect sys_cpu_resetn axi_cpu_interconnect/ARESETN
    ##       ad_connect sys_cpu_resetn axi_cpu_interconnect/S00_ARESETN
    ##       ad_connect axi_cpu_interconnect/S00_AXI sys_ps8/M_AXI_HPM0_LPD
    ##     }
    ##     if {$sys_zynq == 1} {
    ##       ad_connect sys_cpu_clk sys_ps7/M_AXI_GP0_ACLK
    ##       ad_connect sys_cpu_clk axi_cpu_interconnect/ACLK
    ##       ad_connect sys_cpu_clk axi_cpu_interconnect/S00_ACLK
    ##       ad_connect sys_cpu_resetn axi_cpu_interconnect/ARESETN
    ##       ad_connect sys_cpu_resetn axi_cpu_interconnect/S00_ARESETN
    ##       ad_connect axi_cpu_interconnect/S00_AXI sys_ps7/M_AXI_GP0
    ##     }
    ##     if {$sys_zynq == 0} {
    ##       ad_connect sys_cpu_clk axi_cpu_interconnect/ACLK
    ##       ad_connect sys_cpu_clk axi_cpu_interconnect/S00_ACLK
    ##       ad_connect sys_cpu_resetn axi_cpu_interconnect/ARESETN
    ##       ad_connect sys_cpu_resetn axi_cpu_interconnect/S00_ARESETN
    ##       ad_connect axi_cpu_interconnect/S00_AXI sys_mb/M_AXI_DP
    ##     }
    ##   }
    ## 
    ##   if {$sys_zynq == 2} {
    ##     set sys_addr_cntrl_space [get_bd_addr_spaces sys_ps8/Data]
    ##   }
    ##   if {$sys_zynq == 1} {
    ##     set sys_addr_cntrl_space [get_bd_addr_spaces sys_ps7/Data]
    ##   }
    ##   if {$sys_zynq == 0} {
    ##     set sys_addr_cntrl_space [get_bd_addr_spaces sys_mb/Data]
    ##   }
    ## 
    ##   set sys_cpu_interconnect_index [expr $sys_cpu_interconnect_index + 1]
    ## 
    ## 
    ##   set p_cell [get_bd_cells $p_name]
    ##   set p_intf [get_bd_intf_pins -filter "MODE == Slave && VLNV == xilinx.com:interface:aximm_rtl:1.0"\
    ##     -of_objects $p_cell]
    ## 
    ##   set p_hier_cell $p_cell
    ##   set p_hier_intf $p_intf
    ## 
    ##   while {$p_hier_intf != "" && [get_property TYPE $p_hier_cell] == "hier"} {
    ##     set p_hier_intf [find_bd_objs -boundary_type lower \
    ##       -relation connected_to $p_hier_intf]
    ##     if {$p_hier_intf != {}} {
    ##       set p_hier_cell [get_bd_cells -of_objects $p_hier_intf]
    ##     } else {
    ##       set p_hier_cell {}
    ##     }
    ##   }
    ## 
    ##   set p_intf_clock ""
    ##   set p_intf_reset ""
    ## 
    ##   if {$p_hier_cell != {}} {
    ##     set p_intf_name [lrange [split $p_hier_intf "/"] end end]
    ## 
    ##     set p_intf_clock [get_bd_pins -filter "TYPE == clk && \
    ##       (CONFIG.ASSOCIATED_BUSIF == ${p_intf_name} || \
    ##       CONFIG.ASSOCIATED_BUSIF =~ ${p_intf_name}:* || \
    ##       CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name} || \
    ##       CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name}:*)" \
    ##       -quiet -of_objects $p_hier_cell]
    ##     set p_intf_reset [get_bd_pins -filter "TYPE == rst && \
    ##       (CONFIG.ASSOCIATED_BUSIF == ${p_intf_name} || \
    ##        CONFIG.ASSOCIATED_BUSIF =~ ${p_intf_name}:* ||
    ##        CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name} || \
    ##        CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name}:*)" \
    ##        -quiet -of_objects $p_hier_cell]
    ## 
    ##     if {($p_intf_clock ne "") && ($p_intf_reset eq "")} {
    ##       set p_intf_reset [get_property CONFIG.ASSOCIATED_RESET [get_bd_pins ${p_intf_clock}]]
    ##       if {$p_intf_reset ne ""} {
    ##         set p_intf_reset [get_bd_pins -filter "NAME == $p_intf_reset" -of_objects $p_hier_cell]
    ##       }
    ##     }
    ## 
    ##     # Trace back up
    ##     set p_hier_cell2 $p_hier_cell
    ## 
    ##     while {$p_intf_clock != {} && $p_hier_cell2 != $p_cell && $p_hier_cell2 != {}} {
    ##       puts $p_intf_clock
    ##       puts $p_hier_cell2
    ##       set p_intf_clock [find_bd_objs -boundary_type upper \
    ##         -relation connected_to $p_intf_clock]
    ##       if {$p_intf_clock != {}} {
    ##         set p_intf_clock [get_bd_pins [get_property PATH $p_intf_clock]]
    ##         set p_hier_cell2 [get_bd_cells -of_objects $p_intf_clock]
    ##       }
    ##     }
    ## 
    ##     set p_hier_cell2 $p_hier_cell
    ## 
    ##     while {$p_intf_reset != {} && $p_hier_cell2 != $p_cell && $p_hier_cell2 != {}} {
    ##       set p_intf_reset [find_bd_objs -boundary_type upper \
    ##         -relation connected_to $p_intf_reset]
    ##       if {$p_intf_reset != {}} {
    ##         set p_intf_reset [get_bd_pins [get_property PATH $p_intf_reset]]
    ##         set p_hier_cell2 [get_bd_cells -of_objects $p_intf_reset]
    ##       }
    ##     }
    ##   }
    ## 
    ## 
    ##   if {[find_bd_objs -quiet -relation connected_to $p_intf_clock] ne ""} {
    ##     set p_intf_clock ""
    ##   }
    ##   if {$p_intf_reset ne ""} {
    ##     if {[find_bd_objs -quiet -relation connected_to $p_intf_reset] ne ""} {
    ##       set p_intf_reset ""
    ##     }
    ##   }
    ## 
    ##   set_property CONFIG.NUM_MI $sys_cpu_interconnect_index [get_bd_cells axi_cpu_interconnect]
    ## 
    ##   ad_connect sys_cpu_clk axi_cpu_interconnect/${i_str}_ACLK
    ##   if {$p_intf_clock ne ""} {
    ##     ad_connect sys_cpu_clk ${p_intf_clock}
    ##   }
    ##   ad_connect sys_cpu_resetn axi_cpu_interconnect/${i_str}_ARESETN
    ##   if {$p_intf_reset ne ""} {
    ##     ad_connect sys_cpu_resetn ${p_intf_reset}
    ##   }
    ##   ad_connect axi_cpu_interconnect/${i_str}_AXI ${p_intf}
    ## 
    ##   set p_seg [get_bd_addr_segs -of_objects $p_hier_cell]
    ##   set p_index 0
    ##   foreach p_seg_name $p_seg {
    ##     if {$p_index == 0} {
    ##       set p_seg_range [get_property range $p_seg_name]
    ##       if {$p_seg_range < 0x1000} {
    ##         set p_seg_range 0x1000
    ##       }
    ##       if {$sys_zynq == 2} {
    ##         if {($p_address >= 0x40000000) && ($p_address <= 0x4fffffff)} {
    ##           set p_address [expr ($p_address + 0x40000000)]
    ##         }
    ##         if {($p_address >= 0x70000000) && ($p_address <= 0x7fffffff)} {
    ##           set p_address [expr ($p_address + 0x20000000)]
    ##         }
    ##       }
    ##       create_bd_addr_seg -range $p_seg_range \
    ##         -offset $p_address $sys_addr_cntrl_space \
    ##         $p_seg_name "SEG_data_${p_name}"
    ##     } else {
    ##       assign_bd_address $p_seg_name
    ##     }
    ##     incr p_index
    ##   }
    ## }
    ## proc ad_cpu_interrupt {p_ps_index p_mb_index p_name} {
    ## 
    ##   global sys_zynq
    ## 
    ##   if {$sys_zynq == 0} {set p_index_int $p_mb_index}
    ##   if {$sys_zynq >= 1} {set p_index_int $p_ps_index}
    ## 
    ##   set p_index [regsub -all {[^0-9]} $p_index_int ""]
    ##   set m_index [expr ($p_index - 8)]
    ## 
    ##   if {($sys_zynq == 2) && ($p_index <= 7)} {
    ##     set p_net [get_bd_nets -of_objects [get_bd_pins sys_concat_intc_0/In$p_index]]
    ##     set p_pin [get_bd_pins sys_concat_intc_0/In$p_index]
    ## 
    ##     puts "disconnect_bd_net $p_net $p_pin"
    ##     disconnect_bd_net $p_net $p_pin
    ##     ad_connect sys_concat_intc_0/In$p_index $p_name
    ##   }
    ## 
    ##   if {($sys_zynq == 2) && ($p_index >= 8)} {
    ##     set p_net [get_bd_nets -of_objects [get_bd_pins sys_concat_intc_1/In$m_index]]
    ##     set p_pin [get_bd_pins sys_concat_intc_1/In$m_index]
    ## 
    ##     puts "disconnect_bd_net $p_net $p_pin"
    ##     disconnect_bd_net $p_net $p_pin
    ##     ad_connect sys_concat_intc_1/In$m_index $p_name
    ##   }
    ## 
    ##   if {$sys_zynq <= 1} {
    ## 
    ##     set p_net [get_bd_nets -of_objects [get_bd_pins sys_concat_intc/In$p_index]]
    ##     set p_pin [get_bd_pins sys_concat_intc/In$p_index]
    ## 
    ##     puts "disconnect_bd_net $p_net $p_pin"
    ##     disconnect_bd_net $p_net $p_pin
    ##     ad_connect sys_concat_intc/In$p_index $p_name
    ##   }
    ## }
    ## proc stringtohex {str blocksize} {
    ##   binary scan $str H* hex
    ##   return [format %0-[expr $blocksize * 2]s $hex]
    ## }
    ## proc checksum8bit {hex} {
    ## 
    ##   set chks 0
    ##   for {set i 0} {$i < [string length $hex]} {incr i} {
    ##     if { ($i+1) % 2 == 0} {
    ##       set chks [expr $chks + "0x[string range $hex $i-1 $i]"]
    ##     }
    ##   }
    ##   return [format %0.2x [expr 255 - [expr "0x[string range [format %0.2x $chks] [expr [string length [format %0.2x $chks]] -2] [expr [string length [format %0.2x $chks]] -1]]"] +1]]
    ## }
    ## proc hexstr_flip {str} {
    ## 
    ##   set fstr {}
    ##   for {set i 0} {$i < [string length $str]} {incr i} {
    ##     if { ($i+1) % 8 == 0} {
    ##       set line [string range $str [expr $i - 7] $i]
    ##       set fline {}
    ##       for {set j 0} {$j < [string length $line]} {incr j} {
    ##         if { ($j+1) % 2 == 0} {
    ##           append fline [string reverse [append byte [string index $line $j]]]
    ##         } else {
    ##           set byte [string index $line $j]
    ##         }
    ##       }
    ##       append fstr [string reverse $fline]
    ##     }
    ##   }
    ##   return $fstr
    ## }
    ## proc sysid_gen_sys_init_file {{custom_string {}}} {
    ## 
    ##   # git sha
    ##   if {[catch {exec git rev-parse HEAD} gitsha_string] != 0} {
    ##     set gitsha_string 0
    ##   }
    ##   set gitsha_hex [hexstr_flip [stringtohex $gitsha_string 44]]
    ## 
    ##   #git clean
    ##   set git_clean_string "f"
    ##   if {$gitsha_string != 0} {
    ##     if {[catch {exec git status .} gitstat_string] == 0} {
    ##       if [expr [string match *modified $gitstat_string] == 0] {
    ##         set git_clean_string "t"
    ##       }
    ##     }
    ##   }
    ##   set git_clean_hex [hexstr_flip [stringtohex $git_clean_string 4]]
    ## 
    ##   # vadj check
    ##   set vadj_check_string "vadj"
    ##   set vadj_check_hex [hexstr_flip [stringtohex $vadj_check_string 4]]
    ## 
    ##   # time and date
    ##   set thetime [clock seconds]
    ##   set timedate_hex [hexstr_flip [stringtohex $thetime 12]]
    ## 
    ##   # merge components
    ##   set verh_hex {}
    ##   set verh_size 448
    ## 
    ##   append verh_hex $gitsha_hex $git_clean_hex $vadj_check_hex $timedate_hex
    ##   append verh_hex "00000000" [checksum8bit $verh_hex] "000000"
    ##   set verh_hex [format %0-[expr [expr $verh_size] * 8]s $verh_hex]
    ## 
    ##   # common header
    ##   # size in lines
    ##   set table_size 16
    ##   set comh_size [expr 8 * $table_size]
    ## 
    ##   # set version
    ##   set comh_ver_hex "00000001"
    ## 
    ##   set boardname [lindex [split [current_project] _] [expr [llength [split [current_project] _]] - 1]]
    ## 
    ##   # board name
    ##   set boardname_hex [hexstr_flip [stringtohex $boardname 32]]
    ##   
    ##   # project name
    ##   set projname_hex [hexstr_flip [stringtohex [string trimright [string trimright [current_project] $boardname] _] 32]]
    ## 
    ##   # custom string
    ##   set custom_hex [hexstr_flip [stringtohex $custom_string 64]]
    ## 
    ##   # pr offset
    ##   # not used
    ##   set pr_offset "00000000"
    ## 
    ##   # init - generate header
    ##   set comh_hex {}
    ##   append comh_hex $comh_ver_hex
    ## 
    ##   # offset for internal use area
    ##   set offset $table_size
    ##   append comh_hex [format %08s [format %0.2x $offset]]
    ## 
    ##   # offset for projname_hex
    ##   set offset [expr $table_size + $verh_size]
    ##   append comh_hex [format %08s [format %0.2x $offset]]
    ## 
    ##   # offset for boardname_hex
    ##   set offset [expr $offset + [expr [string length $projname_hex] / 8]]
    ##   append comh_hex [format %08s [format %0.2x $offset]]
    ## 
    ##   # offset for custom_hex
    ##   set offset [expr $offset + [expr [string length $boardname_hex] / 8]]
    ##   append comh_hex [format %08s [format %0.2x $offset]]
    ## 
    ##   # offset for pr custom string
    ##   set offset $pr_offset
    ##   append comh_hex [format %08s $offset]
    ## 
    ##   # pad header to match size and add checksum
    ##   set comh_hex [format %0-[expr [expr $table_size - 2] * 8]s $comh_hex]
    ##   append comh_hex "00000000" [checksum8bit $comh_hex] "000000"
    ## 
    ##   # creating file
    ##   set sys_mem_hex [format %0-[expr 512 * 8]s [concat $comh_hex$verh_hex$projname_hex$boardname_hex$custom_hex]]
    ## 
    ##   set sys_mem_file [open "mem_init_sys.txt" "w"]
    ## 
    ##   # writting 32 bits to each line
    ##   for {set i 0} {$i < [string length $sys_mem_hex]} {incr i} {
    ##     if { ($i+1) % 8 == 0} {
    ##       puts $sys_mem_file [string index $sys_mem_hex $i]
    ##     } else {
    ##       puts -nonewline $sys_mem_file [string index $sys_mem_hex $i]
    ##     }
    ##   }
    ##   close $sys_mem_file
    ## }
    ## proc sysid_gen_pr_init_file {custom_string} {
    ## 
    ##   set custom_hex [stringtohex $custom_string 64]
    ## 
    ##   # creating file
    ##   set pr_mem_file [open "mem_init_pr.txt" "w"]
    ## 
    ##   # writting 32 bits to each line
    ##   for {set i 0} {$i < [string length $custom_hex]} {incr i} {
    ##     if { ($i+1) % 8 == 0} {
    ##       puts $pr_mem_file [string index $custom_hex $i]
    ##     } else {
    ##       puts -nonewline $pr_mem_file [string index $custom_hex $i]
    ##     }
    ##   }
    ##   close $pr_mem_file
    ## }
    # adi_project ad9081_fmca_ebz_zcu102 0 [list \
    #   JESD_MODE    8B10B \
    #   RX_JESD_M    8  \
    #   RX_JESD_L    4  \
    #   RX_JESD_S    1  \
    #   RX_JESD_NP   16 \
    #   RX_NUM_LINKS 1  \
    #   TX_JESD_M    8  \
    #   TX_JESD_L    4  \
    #   TX_JESD_S    1  \
    #   TX_JESD_NP   16 \
    #   TX_NUM_LINKS 1  \
    # ]
    WARNING: [Device 21-436] No parts matched 'xczu9eg-ffvb1156-2-e'
    ERROR: [Coretcl 2-106] Specified part could not be found.
    INFO: [Common 17-206] Exiting Vivado at Wed May 15 19:31:35 2024...
    

  • 1. The error+warning is at the bottom of your log. I've seen this before when only webpack is used.

    2. Webpack does not support ZC706 or ZCU102: https://docs.amd.com/r/2020.2-English/ug973-vivado-release-notes-install-license/Supported-Devices The chips won't be in the library, hence the error in both cases.

    -Travis

  • 1. Thanks!  I see it now.

    2.  See below capture of my license manager for VIVADO 19.1.  You can see the part is there at the bottom supported.  When I purchased the ZCU102 Kit there was a license voucher that you had to redeem, which I did.  That's why I'm using the part on the board without a problem.  I have I've also attached the quick start guide that mentions the license voucher (see page 4)

    PDF

  • Hi, following up on this.  Any thoughts?