Category: Hardware
Hi, I have an architecture similar to ADRV9009-ZU11EG Multi-SOM Synchronization(ADRV9009-ZU11EG Multi-SOM Synchronization [Analog Devices Wiki]) now. Clock tree include 1 master HMC7044 and 4 slaver HMC7044, every 7044 provide clock signal to 2 ADRV9009s. We have achieved synchronization of multi-level 7044 output clock signals, and two 9009s under the control of 7044 achieve deterministic delay. But 9009 between 7044 did not achieve deterministic delay.
I would like to ask how rx_sync in hdl/projects/adrv9009zu11eg/adrv2crr_fmcomms8/system_top.v at main · analogdevicesinc/hdl · GitHub is handled, as I can only see the top-level code, thanks.
