I am going through the high speed dma controller to understand it in better way I need documentation like how it works how the arbitration is going inside dma please help me how to get this documenatation.
I am going through the high speed dma controller to understand it in better way I need documentation like how it works how the arbitration is going inside dma please help me how to get this documenatation.
Hi, the documentation is available at analogdevicesinc.github.io/hdl/library/axi_dmac/ (or wiki.analog.com/resources/fpga/docs/axi_dmac (old docs))
Hi JMarques I went through the above link it is mostly about hte pin description and all what is my query is that I need architectural information regarding the blocks inside the DMA can you please provide that?
Hi, beyond what's on the page, there is of course the source code, all the git history, at: https://github.com/analogdevicesinc/hdl/tree/main/library/axi_dmac and a testbench at https://github.com/analogdevicesinc/testbenches/tree/main/dma_loopback
If you have specific questions about it, doesn't hesitate to ask.
Regards,
Jorge
Hi Thanks for your help I am appreciating your efforts my query is that I am going through verilog files of different sub modules inside the axi_dmac for example reset manager I am facing difficulty there becauseI dont have any reference documentation can you please help me to understand those designs through any documentation