Post Go back to editing

JESD204 IQ Packing(Data flow Structure)

Category: Hardware
Product Number: AD9081
We have several questions regarding the use cases of AD9081. 
Sl No Requirement Query
Single ADC/DAC Port should support upto 400 MHz BandWidth. 
Should also support : 
2 X 200MHz
4 X 100MHz
Does AD9081 have support for this?. 
If it does support this requirement, could you provide guidance on configuring the JESD204B interface(Xilinx IP)?
Could you share a reference project for implementing this configuration?
In the case of a 100 MHz bandwidth, we are working with 32-bit IQ samples (16-bit I and 16-bit Q). At the Xilinx JESD204B interface IP, we have four independent AXI data streams for each ADC/DAC. This allows us to receive a 32-bit IQ sample on each clock cycle of the 122.88 MHz clock (lane rate = 4.9152 Gbps).

For the 400 MHz bandwidth case, the line rate becomes 19.6608 Gbps, which is not supported by a single JESD204B line. Therefore, we need to use at least 2 JESD lines. This means the JESD stream interface has to operate at a maximum of 245.76 MHz, which implies that we need to send two IQ samples per clock cycle of 245.76 MHz clock or four IQ samples per clock cycle of 122.88 MHz clock. 

Could you please provide more information on how the IQ samples are packed and transmitted through the JESD stream interface(FPGA side) in the 400 MHz bandwidth case? It would be very helpful if you could connect with your engineering team and share the details on the data flow and any example projects that demonstrate this implementation. Could you please provide information about how to configure the Xilinx JESD Ip for 400 MHz. 
I've attached a reference data flow diagram that explains how 4 IQ samples are sent through the JESD interface, along with the corresponding data flow in the JESD lines. Please review this and let me know if the information is correct or if you have any additional clarifications. It will be really helpful if you can explain the data flow just like the attached image.