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JESD204 IQ Packing(Data flow Structure)

Category: Hardware
Product Number: AD9081
Hi,
We have several questions regarding the use cases of AD9081. 
Sl No Requirement Query
1
Single ADC/DAC Port should support upto 400 MHz BandWidth. 
Should also support : 
2 X 200MHz
4 X 100MHz
Does AD9081 have support for this?. 
If it does support this requirement, could you provide guidance on configuring the JESD204B interface(Xilinx IP)?
Could you share a reference project for implementing this configuration?
In the case of a 100 MHz bandwidth, we are working with 32-bit IQ samples (16-bit I and 16-bit Q). At the Xilinx JESD204B interface IP, we have four independent AXI data streams for each ADC/DAC. This allows us to receive a 32-bit IQ sample on each clock cycle of the 122.88 MHz clock (lane rate = 4.9152 Gbps).

For the 400 MHz bandwidth case, the line rate becomes 19.6608 Gbps, which is not supported by a single JESD204B line. Therefore, we need to use at least 2 JESD lines. This means the JESD stream interface has to operate at a maximum of 245.76 MHz, which implies that we need to send two IQ samples per clock cycle of 245.76 MHz clock or four IQ samples per clock cycle of 122.88 MHz clock. 

Could you please provide more information on how the IQ samples are packed and transmitted through the JESD stream interface(FPGA side) in the 400 MHz bandwidth case? It would be very helpful if you could connect with your engineering team and share the details on the data flow and any example projects that demonstrate this implementation. Could you please provide information about how to configure the Xilinx JESD Ip for 400 MHz. 
I've attached a reference data flow diagram that explains how 4 IQ samples are sent through the JESD interface, along with the corresponding data flow in the JESD lines. Please review this and let me know if the information is correct or if you have any additional clarifications. It will be really helpful if you can explain the data flow just like the attached image.
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  • Hello,

    I'll try to address your questions in order:


    1) Does AD9081 have support for this?

    Yes, you can achieve 4-channel, 100MHz bandwidth with the AD9081. In fact, if you check the system development user guide for this part, at Table 1, you can achieve up to 600MHz instantaneous bandwidth per channel with the 4D4AB model, and up to the full 2GHz bandwidth with the 4D4AC model. Also, check Table 68 of that document (warning: long table) for the supported JESD204B modes.

    2) If it does support this requirement, could you provide guidance on configuring the JESD204B interface(Xilinx IP)?

    Unfortunately, we cannot provide support for Xilinx IP directly. However, if you are using one of our reference designs (in case you are: which one?), we can help. Otherwise, try the Xilinx forums or the official documentation page for their JESD204 IP.

    3) Could you share a reference project for implementing this configuration?

    We do have an reference design for the AD9081-FMCA-EBZ that might help. You can find more information on the quickstart guide for this design.

Reply
  • Hello,

    I'll try to address your questions in order:


    1) Does AD9081 have support for this?

    Yes, you can achieve 4-channel, 100MHz bandwidth with the AD9081. In fact, if you check the system development user guide for this part, at Table 1, you can achieve up to 600MHz instantaneous bandwidth per channel with the 4D4AB model, and up to the full 2GHz bandwidth with the 4D4AC model. Also, check Table 68 of that document (warning: long table) for the supported JESD204B modes.

    2) If it does support this requirement, could you provide guidance on configuring the JESD204B interface(Xilinx IP)?

    Unfortunately, we cannot provide support for Xilinx IP directly. However, if you are using one of our reference designs (in case you are: which one?), we can help. Otherwise, try the Xilinx forums or the official documentation page for their JESD204 IP.

    3) Could you share a reference project for implementing this configuration?

    We do have an reference design for the AD9081-FMCA-EBZ that might help. You can find more information on the quickstart guide for this design.

Children
  • In the case of a 100 MHz bandwidth, we are working with 32-bit IQ samples (16-bit I and 16-bit Q). At the Xilinx JESD204B interface IP, we have four independent AXI data streams for each ADC/DAC. This allows us to receive a 32-bit IQ sample on each clock cycle of the 122.88 MHz clock (lane rate = 4.9152 Gbps).

    For the 400 MHz bandwidth case, the line rate becomes 19.6608 Gbps, which is not supported by a single JESD204B line. Therefore, we need to use at least 2 JESD lines. This means the JESD stream interface has to operate at a maximum of 245.76 MHz, which implies that we need to send two IQ samples per clock cycle of 245.76 MHz clock or four IQ samples per clock cycle of 122.88 MHz clock through the AXi Stream. Since we are working on the IQ Data(32 bit), it will be really helpful if you can provide information how the IQ datas are expected of XCVR/JESD IP(ADI)?. 

    Could you please provide more information on how the IQ samples are packed and transmitted through the JESD stream interface(FPGA side) in the 400 MHz bandwidth case? It would be very helpful if you could share the details on the data flow with any example diagram just like as attached diagram. 
    Right now we are Using this Configurations:- 

    Tx: JESD Mode Number 15  txBW 400.0  Total Int 24  Coarse Int 12  Fine Int 2  Dual Link False  JESD Deframer JESD204B  L 8  M 8  F 2  S 1  K 32  N 16  NP 16  LaneRate 10.0

    Rx: JESD Mode Number 16.00  rxBW 407.0  Total Dec 8  Coarse Dec 4  Fine Dec 2  Dual Link False  JESD Framer JESD204B  Async False  L 8  M 8  F 2  S 1  K 32  NP 16  LaneRate 10.0

    Project:- ad9081_fmca_ebz 

    For example 

  • Hi,

    The ADI transport layer maps the channels as:

    MSB                                                                    LSB
    [ MmSn, ..., MmS1, MnS0, ..., M1Sn, ... M1S1, M1S0, M0Sn, ... M0S1, M0S0 ]


    MmSn representing the m-th converter's n-th sample. You can find more information on the JESD204 ADC Transport IP documentation.

    Additionally, depending on the project configuration, the width of the interface might represent more than one frame - but always an integer multiple number of frames. The ad9081_fmca_ebz project uses by default a datapath of 4 octets per beat per lane for JESD204B, so on that configuration this means there will be 2 frames per beat. In this case, the n-samples above can be more than one, even if the link parameter is S=1.

    The AD9081 maps I/Q samples as separate virtual converters, according to the configurations you set. Please refer to the "MUX 3" section, pg 66 of the User Guide for the ADC side. For the DAC side, please refer to "DATA ROUTER MULTIPLEXERS AND DEFAULT MAPPING", pg 170.


    For your example of RX LMFS=8821, NP=16, 4 I/Q channels, the application interface on the ad9081_fmca_ebz project would therefore be a 256-bit interface, mapped as:

    MSB                                                                                     LSB
    [ Q3S1, Q3S0, I3S1, I3S0, Q2S1, I2S1, I2S0, Q1S1, Q1S0, I1S1, I1S0, Q0S1, Q0S0, I0S1, I0S0]


    Each of those virtual converter samples being of NP=16b wide.


    For the DAC side, things are similar but in the reverse direction.

    Best regards,

    Laez