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Replace one AD-FMCOMMS5 with two AD-FMCOMMS3 boards on a ZC706

Category: Hardware
Product Number: AD-FMCOMMS5

Is it possible to replace one AD-FMCOMMS5 with two AD-FMCOMMS3 boards on a ZC706 and still be able to have 4tx and 4rx working apart from phase sync issues.

Does the zc706 will still boot form sd card and will let set tx and rx parameters in IIO scope?


  • If not possible, then still use zc706 with AD-FMCOMMS3 boot image (i don't know there is two separate boot images for AD-FMCOMMS3 and 5 ) and use two AD-FMCOMMS3 cards one on LPC and another on HPC and access these both from a script in some "context (ip/usb) ?

  • Hi, you have to make a few modifications across all source code to make this work.

    The current fmcomms5/zc706 utilization seem to have room for changes: LUT: 12.44%, DSP: 7.22%

    Before you begin, please read the HDL User Guide and specially the Porting Project page.

    You have to edit the pinout and HDL design to reflect the pinout of the two AD-FMCOMMS3 boards. The file that contains the pinout is fmcomms5/zc706/system_constr.xdc.

    I also recommend to check out the fmcomms2 project since it interfaces an eval board with a single AD9361.

    The fmcomms5 project instantiates two axi_ad9361 IP Cores, so I believe it is possible with minimal modifications.

    In general, HDL related issues do not prevent booting, but will raise warnings that can be checked in dmesg when each respective driver fail to communicate with the IPs through the AXI-memory mapped interfaces.

    See the AD9361 linux driver and the device tree, notice how the devicetree instantiates the ad9361_* twice, indicating that you may not need to modify the software side.

  • thanks for the replay, so taking a AD-FMCOMMS5 project and modality the system_constr.xdc file/pinout to match to the AD-FMCOMMS3 constraints on the second  axi_ad9361 IP Core (to match with the first  axi_ad9361 IP Cores pinout, for the second FMC ) design is the approach i need to take?      

  • Note that FMComms3 cannot be synchronized at the sample level as the MCS (SYNC_IN) pin is grounded on the PCB. Therefore you will not be able to synchronize the digital sections of the part.


  • Yes, pretty much replicate the fmcomms3 pinout on both FMC ports of the fmcomms5 system_constr.xdc file.

    But as Travis pointed, the fmcomms5 are not 2x fmcomms3, and you may need to investigate and apply further changes.

    About the SYNC_IN, it is connected to a 10k pulled-down resistor (R111) and connected to LA19_N H23, thus, you should be able to drive it with the FPGA; but for sure edit the constraint/pinout file to output the mcs_sync(sync_in) on both FMC connectors LA19_N H23 pins.