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AD9209 Core Synchronisation

Category: Hardware
Product Number: AD9209

am using two AD9209, where all x8 Lanes of each data converters shall be used. Logic device is Xilinx FPGA GTY Transceivers

Using a single core to achieve synchronisation is not possible, since a core supports only x8 Lanes.In our case, it is x16 Lanes

To achieve Core Synchronisation. Would you please share the guidelines for both Hardware as well as RTL Perspective

Could you share the Excel for calculating the Variable and Lane Delay of the Link

Do I have to Length Match the Device Clock and SYSREF to the Logic Device and is there any requirement that the Sysref shall be continuous signal not the Single-shot Pulse

Parents Reply
  • Hello, sorry for the delayed response.  By "JESD Mode" I mean I need to know which of the many modes available in the user guide's mode tables you want to use as well as if you plan on using 204B or  a 204C mode.  If the mode must use 8 lanes and must have x18 decimation, that narrows it down to the following:

    • 204B modes: 16.00 or 16.10
    • 204C modes: 17.00 or 17.10 

    Please check those modes in the mode tables (tables 70 and 76) to see if they meet your needs.  Let me know which one is best for you and I can get the latency estimates for you.  If you can also use fewer lanes, more options are available.