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AD9209 Core Synchronisation

Category: Hardware
Product Number: AD9209

am using two AD9209, where all x8 Lanes of each data converters shall be used. Logic device is Xilinx FPGA GTY Transceivers

Using a single core to achieve synchronisation is not possible, since a core supports only x8 Lanes.In our case, it is x16 Lanes

To achieve Core Synchronisation. Would you please share the guidelines for both Hardware as well as RTL Perspective

Could you share the Excel for calculating the Variable and Lane Delay of the Link

Do I have to Length Match the Device Clock and SYSREF to the Logic Device and is there any requirement that the Sysref shall be continuous signal not the Single-shot Pulse

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  • Hi,

    Just letting you know that a part of the people monitoring this forum will be on vacation until next week.
    Since the reply for this questions is not a straight forward one, we will probably come back with and answer then.
    In case you don't get a reply next week, please follow with a reply here. The right person might miss this post.
    Thank you for your understanding.

    Andrei

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  • Hi,

    Just letting you know that a part of the people monitoring this forum will be on vacation until next week.
    Since the reply for this questions is not a straight forward one, we will probably come back with and answer then.
    In case you don't get a reply next week, please follow with a reply here. The right person might miss this post.
    Thank you for your understanding.

    Andrei

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