Hey all I am working on KRIA k26c with a ad9364 transceiver chip. I used the fmcomms2 reference design to build out my custom design. Everything in this design works perfectly but I am having trouble reading the data from the adc_dma. I have a demodulator that takes in 16 bit I data and outputs 16 bits demodulated data. Because of this I made the unpack module 1 channel. (picture below)
Everything before the ADC_FIFO and after the ADC_UPACK is the exact same as the reference design. This includes the adc_dma settings (picture below).
I have ILAs monitoring the data coming out of mu demodulator module and it all looks good. Im trying to use the adi and iio python libraries to read the data and it is somewhat successful. (Code below)
I have a way to send packets and this code only works if i send a packet of 512 bytes every second. But its hard for me to verify if all the packets are being received, I have sync headers i can use to determine the start of the packet and it does not seem like im receiving full packets or all of them. Whenever i do something like send a packet every 5 seconds the rxbuf.refill() command errors out. I could not seem to find out why. Also the reason I am printing like that is becuase after every byte of data that I care about there are 7 bytes of 0x00, which i assume is because my adc dma is 64 bits input/output. I tried changing it to 16 bits input/output but it would error out and i couldnt synthesize the design. All of this to say what is the best way to consistently read all the data being fed to the dma. I am open to making design changes, code changes, etc. Anything helps, I really just need to know how to reliably receive the data so i can use it.
