How to configure JESD204B IP core RBD value

are you referring in ADRV9009 device or FPGA/BBIC device?

FPGA IP core

Moving to FPGA reference design forum for comments .

Hi, please read:

* JESD204B/C Link Configuration, 64b/66b Link latency reduction, register LANEn_LATENCY for the technical documentation topics.

* JESD204B Subclasses—Part 1: An Introduction to JESD204B Subclasses and Deterministic Latency for the discourse on JESD204.

In summary, as illustrated in the waveform at the Link Configuration section, the release opportunity occurs after a fixed number of frame cycles (Receiver Buffer Delay (RBD)), following an LMFC boundary; thus, configure the BUFFER_DELAY field, respecting the value restrictions cited on the provided page.

Regards,

Jorge