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The data_clk of AD9361 is not phase-locked with the reference clock.

Category: Hardware
Product Number: AD936X

I am using a reference clock of 40MHz, and the same clock oscillator generates a PPS signal. My goal is to have the data_clk aligned with the PPS signal (a fixed phase difference) at a sample rate of 40.92 MHz;

I found that when the sampling rate is configured as 40.92MHz, the phase of data_clk observed with an oscilloscope and the PPS signal is not fixed. The data_clk is about 163.6MHz (there may be an error with the oscilloscope). After frequency division by 4, the desired 40.92MHz clock (accurate frequency with oscilloscope) can be obtained. This clock signal cannot be synchronized with the external PPS signal either;

If I set the sampling rate to 40MHz, the aforementioned data_clk is 160MHz, and after frequency division by 4 is 40MHz. In this case, a signal synchronized with the external PPS can be obtained;

I wonder if AD9361 does not support the configuration with a sampling rate of 40.92MHz, or my configuration or reference clock is incorrect;

PS: I use the ADI IIO Oscilloscope software for sample rate configuration. When the sample rate is configured as 40.92MSPS, accurate numbers can be obtained from the software without rounding.