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Errors when running fmcomms2 hdl testbench

Category: Software
Product Number: AD9361
Software Version: HDL 2022_R2

I am trying to run the FPGA simulation 'fmcomms2' available here: github.com/.../README.md

I am using Vivado 2022.2 and successfully built the fmcomms2/zed project for the ZedBoard using the 'hdl' repository and also compiled it with Petalinux. However, when attempting to run the 'testbenches', I encounter validation errors in the Vivado block design (see attached log).

I cloned the testbenches repository as a submodule in the hdl folder, following the instructions, but when executing the tests using the 'make' command, I get 'ERROR: [Coretcl 2-106] Specified part could not be found.'


It seems I might need to specify my project or perform a similar step, but it's not clear to me how to do this. Any guidance on setting up or specifying the project correctly would be very helpful.

Here are the steps I am following:

  1. Clone 'hdl' repo
  2. Checkout 'hdl_2022_R2'
  3. I built the fmcoms2 project for the ZedBoard.
  4. Clone 'testbenches' repo at the root of 'hdl'
  5. Checkout 'tb_2022_R2'
  6. cd testbenches/fmcomms2/
  7. make MODE=gui


    ****** Vivado v2022.2 (64-bit)
      **** SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
      **** IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
        ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    
    source system_project.tcl
    # source ../scripts/adi_sim.tcl
    ## variable adi_sim_defines {}
    ## variable design_name "test_harness"
    ## proc adi_sim_add_define {value} {
    ##   global adi_sim_defines
    ##   lappend adi_sim_defines $value
    ## }
    ## proc adi_sim_project_xilinx {project_name {part "xc7vx485tffg1157-1"}} {
    ##   global design_name
    ##   global ad_project_params
    ##   global use_smartconnect
    ## 
    ##   # Create project
    ##   create_project ${project_name} ./runs/${project_name} -part $part -force
    ## 
    ##   # Set project properties
    ##   set_property -name "default_lib" -value "xil_defaultlib" -objects [current_project]
    ## 
    ##   # Set IP repository paths
    ##   set_property "ip_repo_paths" "[file normalize "./../../library"] " \
    ##     [get_filesets sources_1]
    ## 
    ##   # Rebuild user ip_repo's index before adding any source files
    ##   update_ip_catalog -rebuild
    ## 
    ##   ## Create the bd
    ##   ######################
    ##   create_bd_design $design_name
    ## 
    ##   global sys_zynq
    ##   set sys_zynq -1
    ##   if { ![info exists ad_project_params(CUSTOM_HARNESS)] || !$ad_project_params(CUSTOM_HARNESS) } {
    ##     source ../common/test_harness/test_harness_system_bd.tcl
    ##   }
    ## 
    ##   # transfer tcl parameters as defines to verilog
    ##   foreach {k v} [array get ad_project_params] {
    ##     adi_sim_add_define $k=$v
    ##   }
    ## 
    ##   # Build the test harness based on the topology
    ##   source system_bd.tcl
    ## 
    ##   save_bd_design
    ##   validate_bd_design
    ## 
    ##   # Pass the test harness instance name to the simulation
    ##   adi_sim_add_define "TH=$design_name"
    ## 
    ##   # Use a define for the top module
    ##   adi_sim_add_define "TB=system_tb"
    ## }
    ## proc adi_sim_project_files {project_files} {
    ##   add_files -fileset sim_1 $project_files
    ##   # Set 'sim_1' fileset properties
    ##   set_property -name "top" -value "system_tb" -objects [get_filesets sim_1]
    ## }
    ## proc adi_sim_generate {project_name } {
    ##   global design_name
    ##   global adi_sim_defines
    ## 
    ##   # Set the defines for simulation
    ##   set_property verilog_define $adi_sim_defines [get_filesets sim_1]
    ## 
    ##   set_property -name {xsim.simulate.runtime} -value {} -objects [get_filesets sim_1]
    ## 
    ##   # Show all Xilinx primitives e.g GTYE4_COMMON
    ##   set_property -name {xsim.elaborate.debug_level} -value {all} -objects [get_filesets sim_1]
    ##   # Log all waves
    ##   set_property -name {xsim.simulate.log_all_signals} -value {true} -objects [get_filesets sim_1]
    ## 
    ##   set_property -name {xsim.simulate.xsim.more_options} -value {-sv_seed random} -objects [get_filesets sim_1]
    ## 
    ##   set project_system_dir "./runs/$project_name/$project_name.srcs/sources_1/bd/$design_name"
    ## 
    ##   generate_target Simulation [get_files $project_system_dir/$design_name.bd]
    ## 
    ##   set_property include_dirs . [get_filesets sim_1]
    ## }
    ## proc adi_open_project {project_path} {
    ##   open_project $project_path
    ## }
    ## proc adi_update_define {name value} {
    ##   set defines [get_property verilog_define [get_filesets sim_1]]
    ##   set defines_new {}
    ##   foreach def $defines {
    ##     set def [split $def {=}]
    ##     if {[lindex $def 0] == $name} {
    ##       set def [lreplace $def 1 1 $value]
    ##       puts "reaplacing"
    ##       }
    ##     lappend defines_new "[lindex $def 0]=[lindex $def 1]"
    ##   }
    ##   set_property verilog_define $defines_new [get_filesets sim_1]
    ## 
    ## }
    ## proc adi_project_files {project_files} {
    ## 
    ##   foreach pfile $project_files {
    ##     if {[string range $pfile [expr 1 + [string last . $pfile]] end] == "xdc"} {
    ##       add_files -norecurse -fileset constrs_1 $pfile
    ##     } else {
    ##       add_files -norecurse -fileset sources_1 $pfile
    ##     }
    ##   }
    ## }
    # source ../../scripts/adi_env.tcl
    ## set ad_hdl_dir [file normalize [file join [file dirname [info script]] "../"]]
    ## if [info exists ::env(ADI_HDL_DIR)] {
    ##   set ad_hdl_dir [file normalize $::env(ADI_HDL_DIR)]
    ## }
    ## if [info exists ::env(ADI_GHDL_DIR)] {
    ##   set ad_ghdl_dir [file normalize $::env(ADI_GHDL_DIR)]
    ## }
    ## set required_vivado_version "2022.2"
    ## if {[info exists ::env(REQUIRED_VIVADO_VERSION)]} {
    ##   set required_vivado_version $::env(REQUIRED_VIVADO_VERSION)
    ## } elseif {[info exists REQUIRED_VIVADO_VERSION]} {
    ##   set required_vivado_version $REQUIRED_VIVADO_VERSION
    ## }
    ## if {[info exists ::env(ADI_IGNORE_VERSION_CHECK)]} {
    ##   set IGNORE_VERSION_CHECK 1
    ## } elseif {![info exists IGNORE_VERSION_CHECK]} {
    ##   set IGNORE_VERSION_CHECK 0
    ## }
    ## if {![info exists REQUIRED_QUARTUS_VERSION]} {
    ##   set REQUIRED_QUARTUS_VERSION "22.4.0"
    ## }
    ## proc get_env_param {name default_value} {
    ##   if [info exists ::env($name)] {
    ##     puts "Getting from environment the parameter: $name=$::env($name) "
    ##     return $::env($name)
    ##   } else {
    ##     return $default_value
    ##   }
    ## }
    # source $ad_hdl_dir/projects/scripts/adi_board.tcl
    ## package require math
    ## set sys_cpu_interconnect_index 0
    ## set sys_hpc0_interconnect_index -1
    ## set sys_hpc1_interconnect_index -1
    ## set sys_hp0_interconnect_index -1
    ## set sys_hp1_interconnect_index -1
    ## set sys_hp2_interconnect_index -1
    ## set sys_hp3_interconnect_index -1
    ## set sys_mem_interconnect_index -1
    ## set sys_mem_clk_index 0
    ## set xcvr_index -1
    ## set xcvr_tx_index 0
    ## set xcvr_rx_index 0
    ## set xcvr_instance NONE
    ## proc ad_ip_instance {i_ip i_name {i_params {}}} {
    ## 
    ##   set cell [create_bd_cell -type ip -vlnv [get_ipdefs -all -filter "VLNV =~ *:${i_ip}:* && \
    ##     design_tool_contexts =~ *IPI* && UPGRADE_VERSIONS == \"\""] ${i_name}]
    ##   if {$i_params != {}} {
    ##     set config {}
    ##     # Add CONFIG. prefix to all config options
    ##     foreach {k v} $i_params {
    ##       lappend config "CONFIG.$k" $v
    ##     }
    ##     set_property -dict $config $cell
    ##   }
    ## }
    ## proc ad_ip_parameter {i_name i_param i_value} {
    ## 
    ##   set_property ${i_param} ${i_value} [get_bd_cells ${i_name}]
    ## }
    ## proc ad_connect_type {p_name} {
    ## 
    ##   set m_name ""
    ## 
    ##   if {$m_name eq ""} {set m_name [get_bd_intf_pins  -quiet $p_name]}
    ##   if {$m_name eq ""} {set m_name [get_bd_pins       -quiet $p_name]}
    ##   if {$m_name eq ""} {set m_name [get_bd_intf_ports -quiet $p_name]}
    ##   if {$m_name eq ""} {set m_name [get_bd_ports      -quiet $p_name]}
    ##   if {$m_name eq ""} {set m_name [get_bd_intf_nets  -quiet $p_name]}
    ##   if {$m_name eq ""} {set m_name [get_bd_nets       -quiet $p_name]}
    ## 
    ##   return $m_name
    ## }
    ## proc ad_connect_int_class {p_name} {
    ## 
    ##   set m_name ""
    ## 
    ##   if {$m_name eq ""} {set m_name [get_bd_intf_pins  -quiet $p_name]}
    ##   if {$m_name eq ""} {set m_name [get_bd_pins       -quiet $p_name]}
    ##   # All ports can be handled as pins
    ##   # if {$m_name eq ""} {set m_name [get_bd_intf_ports -quiet $p_name]}
    ##   # if {$m_name eq ""} {set m_name [get_bd_ports      -quiet $p_name]}
    ##   if {$m_name eq ""} {set m_name [get_bd_intf_nets  -quiet $p_name]}
    ##   if {$m_name eq ""} {set m_name [get_bd_nets       -quiet $p_name]}
    ## 
    ##   if {!($m_name eq "")} {
    ##     return [get_property CLASS $m_name]
    ##   }
    ## 
    ##   if {$p_name eq "GND" || $p_name eq "VCC"} {
    ##     return "const"
    ##   }
    ## 
    ##   return "newnet"
    ## }
    ## proc ad_connect_int_get_const {name width} {
    ##   switch $name {
    ##     GND {
    ##       set value 0
    ##     }
    ##     VCC {
    ##       set value [expr (1 << $width) - 1]
    ##     }
    ##     default {
    ##       error "ERROR: ad_connect_int_get_const: Unhandled constant name $name"
    ##     }
    ##   }
    ## 
    ##   set cell_name "$name\_$width"
    ## 
    ##   set cell [get_bd_cells -quiet $cell_name]
    ##   if {$cell eq ""} {
    ##     # Create new constant source
    ##     ad_ip_instance xlconstant $cell_name
    ##     set cell [get_bd_cells -quiet $cell_name]
    ##     set_property CONFIG.CONST_WIDTH $width $cell
    ##     set_property CONFIG.CONST_VAL $value $cell
    ##   }
    ## 
    ##   return $cell
    ## }
    ## proc ad_connect_int_width {obj} {
    ##   if {$obj eq ""} {
    ##     error "ERROR: ad_connect_int_width: No object provided."
    ##   }
    ## 
    ##   set classname [get_property -quiet CLASS $obj]
    ##   if {$classname eq ""} {
    ##     error "ERROR: ad_connect_int_width: Cannot determine width of class-less object: $obj"
    ##   }
    ##   if {[string first intf $classname] != -1} {
    ##     error "ERROR: ad_connect_int_width: Cannot determine width of interface object: $obj ($classname)"
    ##   }
    ## 
    ##   if {([get_property -quiet LEFT $obj] eq "") || ([get_property -quiet RIGHT $obj] eq "")} {
    ##     return 1
    ##   }
    ## 
    ##   set left [get_property LEFT $obj]
    ##   set right [get_property RIGHT $obj]
    ## 
    ##   set high [::math::max $left $right]
    ##   set low [::math::min $left $right]
    ## 
    ##   return [expr {1 + $high - $low}]
    ## }
    ## proc ad_connect {name_a name_b} {
    ##   set type_a [ad_connect_int_class $name_a]
    ##   set type_b [ad_connect_int_class $name_b]
    ## 
    ##   set obj_a [ad_connect_type $name_a]
    ##   set obj_b [ad_connect_type $name_b]
    ## 
    ##   if {!([string first intf $type_a]+1) != !([string first intf $type_b]+1)} {
    ##     error "ERROR: ad_connect: Cannot connect non-interface to interface: $name_a ($type_a) <-/-> $name_b ($type_b)"
    ##   }
    ## 
    ##   switch $type_a,$type_b {
    ##     newnet,newnet {
    ##       error "ERROR: ad_connect: Cannot create connection between two new nets: $name_a <-/-> $name_b"
    ##     }
    ##     const,const {
    ##       error "ERROR: ad_connect: Cannot connect constant to constant: $name_a <-/-> $name_b"
    ##     }
    ##     bd_net,bd_net -
    ##     bd_intf_net,bd_intf_net {
    ##       error "ERROR: ad_connect: Cannot connect (intf) net to (intf) net: $name_a ($type_a) <-/-> $name_b ($type_b)"
    ##     }
    ##     bd_net,newnet -
    ##     newnet,bd_net {
    ##       error "ERROR: ad_connect: Cannot connect existing net to new net: $name_a ($type_a) <-/-> $name_b ($type_b)"
    ##     }
    ##     const,newnet -
    ##     newnet,const {
    ##       error "ERROR: ad_connect: Cannot connect new network to constant, instead you should connect to the constant directly: $name_a ($type_a) <-/-> $name_b ($type_b)"
    ##     }
    ## 
    ##     bd_pin,bd_pin {
    ##       connect_bd_net $obj_a $obj_b
    ##       puts "connect_bd_net $obj_a $obj_b"
    ##       return
    ##     }
    ##     bd_net,bd_pin {
    ##       connect_bd_net -net $obj_a $obj_b
    ##       puts "connect_bd_net -net $obj_a $obj_b"
    ##       return
    ##     }
    ##     bd_pin,bd_net {
    ##       connect_bd_net -net $obj_b $obj_a
    ##       puts "connect_bd_net -net $obj_b $obj_a"
    ##       return
    ##     }
    ##     bd_pin,newnet {
    ##       connect_bd_net -net $name_b $obj_a
    ##       puts "connect_bd_net -net $name_b $obj_a"
    ##       return
    ##     }
    ##     newnet,bd_pin {
    ##       connect_bd_net -net $name_a $obj_b
    ##       puts "connect_bd_net -net $name_a $obj_b"
    ##       return
    ##     }
    ##     bd_intf_pin,bd_intf_pin {
    ##       connect_bd_intf_net $obj_a $obj_b
    ##       puts "connect_bd_intf_net $obj_a $obj_b"
    ##       return
    ##     }
    ##     const,bd_pin -
    ##     const,bd_net {
    ##       # Handled after the switch statement
    ##     }
    ##     bd_net,const -
    ##     bd_pin,const {
    ##       # Swap vars
    ##       set tmp $obj_a
    ##       set obj_a $obj_b
    ##       set obj_b $tmp
    ##       set tmp $name_a
    ##       set name_a $name_b
    ##       set name_b $tmp
    ##       # Handled after the switch statement
    ##     }
    ##     default {
    ##       error "ERROR: ad_connect: Cannot connect, case unhandled: $name_a ($type_a) <-/-> $name_b ($type_b)"
    ##     }
    ##   }
    ## 
    ##   # Continue working on nets that connect to constant. obj_b is the net/pin
    ##   set width [ad_connect_int_width $obj_b]
    ##   set cell [ad_connect_int_get_const $name_a $width]
    ##   connect_bd_net [get_bd_pin $cell/dout] $obj_b
    ##   puts "connect_bd_net [get_bd_pin $cell/dout] $obj_b"
    ## }
    ## proc ad_disconnect {p_name_1 p_name_2} {
    ## 
    ##   set m_name_1 [ad_connect_type $p_name_1]
    ##   set m_name_2 [ad_connect_type $p_name_2]
    ## 
    ##   if {[get_property CLASS $m_name_1] eq "bd_net"} {
    ##     disconnect_bd_net $m_name_1 $m_name_2
    ##     return
    ##   }
    ## 
    ##   if {[get_property CLASS $m_name_1] eq "bd_port"} {
    ##     delete_bd_objs -quiet [get_bd_nets -quiet -of_objects \
    ##       [find_bd_objs -relation connected_to $m_name_1]]
    ##     delete_bd_objs -quiet $m_name_1
    ##     return
    ##   }
    ## 
    ##   if {[get_property CLASS $m_name_1] eq "bd_pin"} {
    ##     delete_bd_objs -quiet [get_bd_nets -quiet -of_objects \
    ##       [find_bd_objs -relation connected_to $m_name_1]]
    ##     delete_bd_objs -quiet $m_name_1
    ##     return
    ##   }
    ## }
    ## proc ad_xcvrcon {u_xcvr a_xcvr a_jesd {lane_map {}} {link_clk {}} {device_clk {}} {num_of_max_lanes -1} {partial_lane_map {}} {connect_empty_lanes 1}} {
    ## 
    ##   global xcvr_index
    ##   global xcvr_tx_index
    ##   global xcvr_rx_index
    ##   global xcvr_instance
    ## 
    ##   set qpll_enable [get_property CONFIG.QPLL_ENABLE [get_bd_cells $a_xcvr]]
    ##   set tx_or_rx_n [get_property CONFIG.TX_OR_RX_N [get_bd_cells $a_xcvr]]
    ## 
    ##   set xcvr_type [get_property CONFIG.XCVR_TYPE [get_bd_cells $u_xcvr]]
    ## 
    ##   set link_mode_u [get_property CONFIG.LINK_MODE [get_bd_cells $u_xcvr]]
    ##   set link_mode_a [get_property CONFIG.LINK_MODE [get_bd_cells $a_xcvr]]
    ## 
    ##   if {$link_mode_u != $link_mode_a} {
    ##      puts "CRITICAL WARNING: LINK_MODE parameter mismatch between $u_xcvr ($link_mode_u) and $a_xcvr ($link_mode_a)"
    ##   }
    ##   set link_mode $link_mode_u
    ## 
    ##   set jesd204_bd_type [get_property TYPE [get_bd_cells $a_jesd]]
    ## 
    ##   if {$jesd204_bd_type == "hier"} {
    ##     set jesd204_type 0
    ##   } else {
    ##     set jesd204_type 1
    ##   }
    ## 
    ##   if {$xcvr_instance ne $u_xcvr} {
    ##     set xcvr_index [expr ($xcvr_index + 1)]
    ##     set xcvr_tx_index 0
    ##     set xcvr_rx_index 0
    ##     set xcvr_instance $u_xcvr
    ##   }
    ## 
    ##   set txrx "rx"
    ##   set data_dir "I"
    ##   set ctrl_dir "O"
    ##   set index $xcvr_rx_index
    ## 
    ##   if {$tx_or_rx_n == 1} {
    ## 
    ##     set txrx "tx"
    ##     set data_dir "O"
    ##     set ctrl_dir "I"
    ##     set index $xcvr_tx_index
    ##   }
    ## 
    ##   set m_sysref ${txrx}_sysref_${index}
    ##   set m_sync ${txrx}_sync_${index}
    ##   set m_data ${txrx}_data
    ## 
    ##   if {$xcvr_index >= 1} {
    ## 
    ##     set m_sysref ${txrx}_sysref_${xcvr_index}_${index}
    ##     set m_sync ${txrx}_sync_${xcvr_index}_${index}
    ##     set m_data ${txrx}_data_${xcvr_index}
    ##   }
    ## 
    ##   if {$jesd204_type == 0} {
    ##     set num_of_links [get_property CONFIG.NUM_LINKS [get_bd_cells $a_jesd/$txrx]]
    ##   } else {
    ##     set num_of_links 1
    ##   }
    ## 
    ##   set no_of_lanes [get_property CONFIG.NUM_LANES [get_bd_cells $a_jesd/$txrx]]
    ##   set max_no_of_lanes $no_of_lanes
    ## 
    ##   if {$num_of_max_lanes != -1} {
    ##     set max_no_of_lanes $num_of_max_lanes
    ##   }
    ##   create_bd_port -dir I $m_sysref
    ##   create_bd_port -from [expr $num_of_links - 1] -to 0 -dir ${ctrl_dir} $m_sync
    ## 
    ##   set use_2x_clk 0
    ##   if {$link_clk == {}} {
    ##     # For 204C modes on GTH a 2x clock is required to drive the PCS
    ##     # In such case set the xcvr out clock to be the double of the lane rate/66(40)
    ##     # and use the secondary div2 clock output for the link clock
    ##     if {$link_mode == 2 && ($xcvr_type == 5 || $xcvr_type == 8)} {
    ##       set link_clk ${u_xcvr}/${txrx}_out_clk_div2_${index}
    ##       set link_clk_2x ${u_xcvr}/${txrx}_out_clk_${index}
    ##       set use_2x_clk 1
    ##     } else {
    ##       if {$partial_lane_map != {}} {
    ##         set cur_index [lindex $partial_lane_map $index]
    ##         set link_clk ${u_xcvr}/${txrx}_out_clk_${cur_index}
    ##       } else {
    ##         set link_clk ${u_xcvr}/${txrx}_out_clk_${index}
    ##       }
    ##     }
    ##     set rst_gen [regsub -all "/" ${a_jesd}_rstgen "_"]
    ##     set create_rst_gen 1
    ##   } else {
    ##     set rst_gen ${link_clk}_rstgen
    ##     # Only create one reset gen per clock
    ##     set create_rst_gen [expr {[get_bd_cells -quiet ${rst_gen}] == {}}]
    ##   }
    ## 
    ##   if {$device_clk == {}} {
    ##     set device_clk $link_clk
    ##   } else {
    ##     set rst_gen ${device_clk}_rstgen
    ##     # Only create one reset gen per clock
    ##     set create_rst_gen [expr {[get_bd_cells -quiet ${rst_gen}] == {}}]
    ##   }
    ## 
    ##   if {${create_rst_gen}} {
    ##     ad_ip_instance proc_sys_reset ${rst_gen}
    ##     ad_connect ${device_clk} ${rst_gen}/slowest_sync_clk
    ##     ad_connect sys_cpu_resetn ${rst_gen}/ext_reset_in
    ##   }
    ## 
    ##   if {$partial_lane_map != {}} {
    ##     for {set n 0} {$n < $no_of_lanes} {incr n} {
    ## 
    ##       set phys_lane [lindex $partial_lane_map $n]
    ## 
    ##       if {$phys_lane != {}} {
    ##         if {$jesd204_type == 0} {
    ##           ad_connect  ${u_xcvr}/${txrx}_${phys_lane} ${a_jesd}/${txrx}_phy${n}
    ##         } else {
    ##           ad_connect  ${u_xcvr}/${txrx}_${phys_lane} ${a_jesd}/gt${n}_${txrx}
    ##         }
    ##       }
    ## 
    ##       if {$tx_or_rx_n == 0} {
    ##         if {$jesd204_type == 0} {
    ##           if {$link_mode == 1} {
    ##             ad_connect  ${a_jesd}/phy_en_char_align ${u_xcvr}/${txrx}_calign_${phys_lane}
    ##           }
    ##         } else {
    ##           ad_connect  ${a_jesd}/rxencommaalign_out ${u_xcvr}/${txrx}_calign_${phys_lane}
    ##         }
    ##       }
    ##     }
    ##     if {$connect_empty_lanes == 1} {
    ##       for {set n 0} {$n < $max_no_of_lanes} {incr n} {
    ## 
    ##         set m [expr ($n + $index)]
    ## 
    ##         if {$lane_map != {}} {
    ##           set phys_lane [lindex $lane_map $n]
    ##         } else {
    ##           set phys_lane $m
    ##         }
    ## 
    ##         if {$tx_or_rx_n == 0} {
    ##           ad_connect  ${a_xcvr}/up_es_${n} ${u_xcvr}/up_es_${phys_lane}
    ##         }
    ## 
    ##         if {(($n%4) == 0) && ($qpll_enable == 1)} {
    ##           ad_connect  ${a_xcvr}/up_cm_${n} ${u_xcvr}/up_cm_${m}
    ##         }
    ##         ad_connect  ${a_xcvr}/up_ch_${n} ${u_xcvr}/up_${txrx}_${phys_lane}
    ##         ad_connect  ${link_clk} ${u_xcvr}/${txrx}_clk_${phys_lane}
    ##         if {$use_2x_clk == 1} {
    ##           ad_connect  ${link_clk_2x} ${u_xcvr}/${txrx}_clk_2x_${phys_lane}
    ##         }
    ## 
    ##         create_bd_port -dir ${data_dir} ${m_data}_${m}_p
    ##         create_bd_port -dir ${data_dir} ${m_data}_${m}_n
    ##         ad_connect  ${u_xcvr}/${txrx}_${m}_p ${m_data}_${m}_p
    ##         ad_connect  ${u_xcvr}/${txrx}_${m}_n ${m_data}_${m}_n
    ##       }
    ##     } else {
    ##       ## Do nothing, the connections will be done manually
    ##     }
    ## 
    ##   } else {
    ##     for {set n 0} {$n < $no_of_lanes} {incr n} {
    ## 
    ##       set m [expr ($n + $index)]
    ##       if {$lane_map != {}} {
    ##         set phys_lane [lindex $lane_map $n]
    ##       } else {
    ##         set phys_lane $m
    ##       }
    ## 
    ##       if {$tx_or_rx_n == 0} {
    ##         ad_connect  ${a_xcvr}/up_es_${n} ${u_xcvr}/up_es_${phys_lane}
    ##         if {$jesd204_type == 0} {
    ##           if {$link_mode == 1} {
    ##             ad_connect  ${a_jesd}/phy_en_char_align ${u_xcvr}/${txrx}_calign_${phys_lane}
    ##           }
    ##         } else {
    ##           ad_connect  ${a_jesd}/rxencommaalign_out ${u_xcvr}/${txrx}_calign_${phys_lane}
    ##         }
    ##       }
    ## 
    ##       if {(($n%4) == 0) && ($qpll_enable == 1)} {
    ##         ad_connect  ${a_xcvr}/up_cm_${n} ${u_xcvr}/up_cm_${m}
    ##       }
    ##       ad_connect  ${a_xcvr}/up_ch_${n} ${u_xcvr}/up_${txrx}_${phys_lane}
    ##       ad_connect  ${link_clk} ${u_xcvr}/${txrx}_clk_${phys_lane}
    ##       if {$use_2x_clk == 1} {
    ##         ad_connect  ${link_clk_2x} ${u_xcvr}/${txrx}_clk_2x_${phys_lane}
    ##       }
    ##       if {$phys_lane != {}} {
    ##         if {$jesd204_type == 0} {
    ##           ad_connect  ${u_xcvr}/${txrx}_${phys_lane} ${a_jesd}/${txrx}_phy${n}
    ##         } else {
    ##           ad_connect  ${u_xcvr}/${txrx}_${phys_lane} ${a_jesd}/gt${n}_${txrx}
    ##         }
    ##       }
    ## 
    ##       create_bd_port -dir ${data_dir} ${m_data}_${m}_p
    ##       create_bd_port -dir ${data_dir} ${m_data}_${m}_n
    ##       ad_connect  ${u_xcvr}/${txrx}_${m}_p ${m_data}_${m}_p
    ##       ad_connect  ${u_xcvr}/${txrx}_${m}_n ${m_data}_${m}_n
    ##     }
    ## 
    ##     for {set n $no_of_lanes} {$n < $max_no_of_lanes} {incr n} {
    ## 
    ##       set m [expr ($n + $index)]
    ## 
    ##       if {$lane_map != {}} {
    ##         set phys_lane [lindex $lane_map $n]
    ##       } else {
    ##         set phys_lane $m
    ##       }
    ## 
    ##       create_bd_port -dir ${data_dir} ${m_data}_${m}_p
    ##       create_bd_port -dir ${data_dir} ${m_data}_${m}_n
    ##       ad_connect  ${u_xcvr}/${txrx}_${m}_p ${m_data}_${m}_p
    ##       ad_connect  ${u_xcvr}/${txrx}_${m}_n ${m_data}_${m}_n
    ##       ad_connect  ${link_clk} ${u_xcvr}/${txrx}_clk_${phys_lane}
    ## 
    ##       if {$tx_or_rx_n == 0} {
    ##         if {$jesd204_type == 0} {
    ##           if {$link_mode == 1} {
    ## 	    ad_connect  ${a_jesd}/phy_en_char_align ${u_xcvr}/${txrx}_calign_${phys_lane}
    ##           }
    ## 	}
    ##       }
    ##     }
    ##   }
    ## 
    ##   if {$jesd204_type == 0} {
    ##     ad_connect  ${a_jesd}/sysref $m_sysref
    ##     if {$link_mode == 1} {
    ##       ad_connect  ${a_jesd}/sync $m_sync
    ##     }
    ##     ad_connect  ${device_clk} ${a_jesd}/device_clk
    ##     ad_connect  ${link_clk} ${a_jesd}/link_clk
    ##   } else {
    ##     ad_connect  ${a_jesd}/${txrx}_sysref $m_sysref
    ##     ad_connect  ${a_jesd}/${txrx}_sync $m_sync
    ##     ad_connect  ${device_clk} ${a_jesd}/${txrx}_core_clk
    ##     ad_connect  ${a_xcvr}/up_status ${a_jesd}/${txrx}_reset_done
    ##     ad_connect  ${rst_gen}/peripheral_reset ${a_jesd}/${txrx}_reset
    ##   }
    ## 
    ##   if {$tx_or_rx_n == 0} {
    ##     set xcvr_rx_index [expr ($xcvr_rx_index + $max_no_of_lanes)]
    ##   }
    ## 
    ##   if {$tx_or_rx_n == 1} {
    ##     set xcvr_tx_index [expr ($xcvr_tx_index + $max_no_of_lanes)]
    ##   }
    ## }
    ## proc ad_xcvrpll {m_src m_dst} {
    ## 
    ##   foreach p_dst [get_bd_pins -quiet $m_dst] {
    ##     connect_bd_net [ad_connect_type $m_src] $p_dst
    ##   }
    ## }
    ## proc ad_mem_hpc0_interconnect {p_clk p_name} {
    ## 
    ##   global sys_zynq
    ## 
    ##   if {$sys_zynq == 2} {ad_mem_hpx_interconnect "HPC0" $p_clk $p_name}
    ## }
    ## proc ad_mem_hpc1_interconnect {p_clk p_name} {
    ## 
    ##   global sys_zynq
    ## 
    ##   if {$sys_zynq == 2} {ad_mem_hpx_interconnect "HPC1" $p_clk $p_name}
    ## }
    ## proc ad_mem_hp0_interconnect {p_clk p_name} {
    ## 
    ##   global sys_zynq
    ## 
    ##   if {($sys_zynq != 1 && $sys_zynq != 2) && ($p_name eq "sys_ps7/S_AXI_HP0")} {return}
    ##   if {$sys_zynq == -1} {ad_mem_hpx_interconnect "SIM" $p_clk $p_name}
    ##   if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
    ##   if {$sys_zynq == 1} {ad_mem_hpx_interconnect "HP0" $p_clk $p_name}
    ##   if {$sys_zynq == 2} {ad_mem_hpx_interconnect "HP0" $p_clk $p_name}
    ##   if {$sys_zynq == 3} {ad_mem_hpx_interconnect "NOC" $p_clk $p_name}
    ## }
    ## proc ad_mem_hp1_interconnect {p_clk p_name} {
    ## 
    ##   global sys_zynq
    ## 
    ##   if {($sys_zynq != 1 && $sys_zynq != 2) && ($p_name eq "sys_ps7/S_AXI_HP1")} {return}
    ##   if {$sys_zynq == -1} {ad_mem_hpx_interconnect "SIM" $p_clk $p_name}
    ##   if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
    ##   if {$sys_zynq == 1} {ad_mem_hpx_interconnect "HP1" $p_clk $p_name}
    ##   if {$sys_zynq == 2} {ad_mem_hpx_interconnect "HP1" $p_clk $p_name}
    ##   if {$sys_zynq == 3} {ad_mem_hpx_interconnect "NOC" $p_clk $p_name}
    ## }
    ## proc ad_mem_hp2_interconnect {p_clk p_name} {
    ## 
    ##   global sys_zynq
    ## 
    ##   if {($sys_zynq != 1 && $sys_zynq != 2) && ($p_name eq "sys_ps7/S_AXI_HP2")} {return}
    ##   if {$sys_zynq == -1} {ad_mem_hpx_interconnect "SIM" $p_clk $p_name}
    ##   if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
    ##   if {$sys_zynq == 1} {ad_mem_hpx_interconnect "HP2" $p_clk $p_name}
    ##   if {$sys_zynq == 2} {ad_mem_hpx_interconnect "HP2" $p_clk $p_name}
    ##   if {$sys_zynq == 3} {ad_mem_hpx_interconnect "NOC" $p_clk $p_name}
    ## }
    ## proc ad_mem_hp3_interconnect {p_clk p_name} {
    ## 
    ##   global sys_zynq
    ## 
    ##   if {($sys_zynq != 1 && $sys_zynq != 2) && ($p_name eq "sys_ps7/S_AXI_HP3")} {return}
    ##   if {$sys_zynq == -1} {ad_mem_hpx_interconnect "SIM" $p_clk $p_name}
    ##   if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name}
    ##   if {$sys_zynq == 1} {ad_mem_hpx_interconnect "HP3" $p_clk $p_name}
    ##   if {$sys_zynq == 2} {ad_mem_hpx_interconnect "HP3" $p_clk $p_name}
    ##   if {$sys_zynq == 3} {ad_mem_hpx_interconnect "NOC" $p_clk $p_name}
    ## }
    ## proc ad_mem_hpx_interconnect {p_sel p_clk p_name} {
    ## 
    ##   global sys_zynq
    ##   global sys_ddr_addr_seg
    ##   global sys_hpc0_interconnect_index
    ##   global sys_hpc1_interconnect_index
    ##   global sys_hp0_interconnect_index
    ##   global sys_hp1_interconnect_index
    ##   global sys_hp2_interconnect_index
    ##   global sys_hp3_interconnect_index
    ##   global sys_mem_interconnect_index
    ##   global sys_mem_clk_index
    ## 
    ##   set p_name_int $p_name
    ##   set p_clk_source [get_bd_pins -filter {DIR == O} -of_objects [get_bd_nets $p_clk]]
    ## 
    ##   if {$p_sel eq "SIM"} {
    ##     if {$sys_mem_interconnect_index < 0} {
    ##       ad_ip_instance smartconnect axi_mem_interconnect
    ##     }
    ##     set m_interconnect_index $sys_mem_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_mem_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs -of_objects [get_bd_cells ddr_axi_vip]]
    ##   }
    ## 
    ##   if {$p_sel eq "MEM"} {
    ##     if {$sys_mem_interconnect_index < 0} {
    ##       ad_ip_instance smartconnect axi_mem_interconnect
    ##     }
    ##     set m_interconnect_index $sys_mem_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_mem_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs -of_objects [get_bd_cells axi_ddr_cntrl] -filter "USAGE == memory"]
    ##   }
    ## 
    ##   if {($p_sel eq "HP0") && ($sys_zynq == 1)} {
    ##     if {$sys_hp0_interconnect_index < 0} {
    ##       set p_name_int sys_ps7/S_AXI_HP0
    ##       set_property CONFIG.PCW_USE_S_AXI_HP0 {1} [get_bd_cells sys_ps7]
    ##       ad_ip_instance smartconnect axi_hp0_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hp0_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hp0_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP0/HP0_DDR_LOWOCM]
    ##   }
    ## 
    ##   if {($p_sel eq "HP1") && ($sys_zynq == 1)} {
    ##     if {$sys_hp1_interconnect_index < 0} {
    ##       set p_name_int sys_ps7/S_AXI_HP1
    ##       set_property CONFIG.PCW_USE_S_AXI_HP1 {1} [get_bd_cells sys_ps7]
    ##       ad_ip_instance smartconnect axi_hp1_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hp1_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hp1_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM]
    ##   }
    ## 
    ##   if {($p_sel eq "HP2") && ($sys_zynq == 1)} {
    ##     if {$sys_hp2_interconnect_index < 0} {
    ##       set p_name_int sys_ps7/S_AXI_HP2
    ##       set_property CONFIG.PCW_USE_S_AXI_HP2 {1} [get_bd_cells sys_ps7]
    ##       ad_ip_instance smartconnect axi_hp2_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hp2_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hp2_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM]
    ##   }
    ## 
    ##   if {($p_sel eq "HP3") && ($sys_zynq == 1)} {
    ##     if {$sys_hp3_interconnect_index < 0} {
    ##       set p_name_int sys_ps7/S_AXI_HP3
    ##       set_property CONFIG.PCW_USE_S_AXI_HP3 {1} [get_bd_cells sys_ps7]
    ##       ad_ip_instance smartconnect axi_hp3_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hp3_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hp3_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM]
    ##   }
    ## 
    ##   if {($p_sel eq "HPC0") && ($sys_zynq == 2)} {
    ##     if {$sys_hpc0_interconnect_index < 0} {
    ##       set p_name_int sys_ps8/S_AXI_HPC0_FPD
    ##       set_property CONFIG.PSU__USE__S_AXI_GP0 {1} [get_bd_cells sys_ps8]
    ##       set_property CONFIG.PSU__AFI0_COHERENCY {1} [get_bd_cells sys_ps8]
    ##       ad_ip_instance smartconnect axi_hpc0_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hpc0_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hpc0_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps8/SAXIGP0/HPC0_DDR_*]
    ##   }
    ## 
    ##   if {($p_sel eq "HPC1") && ($sys_zynq == 2)} {
    ##     if {$sys_hpc1_interconnect_index < 0} {
    ##       set p_name_int sys_ps8/S_AXI_HPC1_FPD
    ##       set_property CONFIG.PSU__USE__S_AXI_GP1 {1} [get_bd_cells sys_ps8]
    ##       set_property CONFIG.PSU__AFI1_COHERENCY {1} [get_bd_cells sys_ps8]
    ##       ad_ip_instance smartconnect axi_hpc1_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hpc1_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hpc1_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps8/SAXIGP1/HPC1_DDR_*]
    ##   }
    ## 
    ##   if {($p_sel eq "HP0") && ($sys_zynq == 2)} {
    ##     if {$sys_hp0_interconnect_index < 0} {
    ##       set p_name_int sys_ps8/S_AXI_HP0_FPD
    ##       set_property CONFIG.PSU__USE__S_AXI_GP2 {1} [get_bd_cells sys_ps8]
    ##       ad_ip_instance smartconnect axi_hp0_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hp0_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hp0_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps8/SAXIGP2/HP0_DDR_*]
    ##   }
    ## 
    ##   if {($p_sel eq "HP1") && ($sys_zynq == 2)} {
    ##     if {$sys_hp1_interconnect_index < 0} {
    ##       set p_name_int sys_ps8/S_AXI_HP1_FPD
    ##       set_property CONFIG.PSU__USE__S_AXI_GP3 {1} [get_bd_cells sys_ps8]
    ##       ad_ip_instance smartconnect axi_hp1_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hp1_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hp1_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps8/SAXIGP3/HP1_DDR_*]
    ##   }
    ## 
    ##   if {($p_sel eq "HP2") && ($sys_zynq == 2)} {
    ##     if {$sys_hp2_interconnect_index < 0} {
    ##       set p_name_int sys_ps8/S_AXI_HP2_FPD
    ##       set_property CONFIG.PSU__USE__S_AXI_GP4 {1} [get_bd_cells sys_ps8]
    ##       ad_ip_instance smartconnect axi_hp2_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hp2_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hp2_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps8/SAXIGP4/HP2_DDR_*]
    ##   }
    ## 
    ##   if {($p_sel eq "HP3") && ($sys_zynq == 2)} {
    ##     if {$sys_hp3_interconnect_index < 0} {
    ##       set p_name_int sys_ps8/S_AXI_HP3_FPD
    ##       set_property CONFIG.PSU__USE__S_AXI_GP5 {1} [get_bd_cells sys_ps8]
    ##       ad_ip_instance smartconnect axi_hp3_interconnect
    ##     }
    ##     set m_interconnect_index $sys_hp3_interconnect_index
    ##     set m_interconnect_cell [get_bd_cells axi_hp3_interconnect]
    ##     set m_addr_seg [get_bd_addr_segs sys_ps8/SAXIGP5/HP3_DDR_*]
    ##   }
    ## 
    ##   if {$p_sel eq "NOC"} {
    ##     set m_interconnect_index [get_property CONFIG.NUM_SI [get_bd_cells axi_noc_0]]
    ##     set m_interconnect_cell [get_bd_cells axi_noc_0]
    ##     set m_addr_seg [get_bd_addr_segs  axi_noc_0/S[format "%02s" [expr $m_interconnect_index +1]]_AXI/C0_DDR_LOW0]
    ##     set sys_mem_clk_index [expr [get_property CONFIG.NUM_CLKS [get_bd_cells axi_noc_0]]-1]
    ##   }
    ## 
    ##   set i_str "S$m_interconnect_index"
    ##   if {$m_interconnect_index < 10} {
    ##     set i_str "S0$m_interconnect_index"
    ##   }
    ## 
    ##   set m_interconnect_index [expr $m_interconnect_index + 1]
    ## 
    ##   set p_intf_name [lrange [split $p_name_int "/"] end end]
    ##   set p_cell_name [lrange [split $p_name_int "/"] 0 0]
    ##   set p_intf_clock [get_bd_pins -filter "TYPE == clk && (CONFIG.ASSOCIATED_BUSIF == ${p_intf_name} || \
    ##     CONFIG.ASSOCIATED_BUSIF =~ ${p_intf_name}:* || CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name} || \
    ##     CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name}:*)" -quiet -of_objects [get_bd_cells $p_cell_name]]
    ##   if {[find_bd_objs -quiet -relation connected_to $p_intf_clock] ne "" ||
    ##       $p_intf_clock eq $p_clk_source} {
    ##     set p_intf_clock ""
    ##   }
    ## 
    ##   regsub clk $p_clk resetn p_rst
    ##   if {[get_bd_nets -quiet $p_rst] eq ""} {
    ##     set p_rst sys_cpu_resetn
    ##   }
    ## 
    ##   if {$m_interconnect_index == 0} {
    ##     set_property CONFIG.NUM_MI 1 $m_interconnect_cell
    ##     set_property CONFIG.NUM_SI 1 $m_interconnect_cell
    ##     ad_connect $p_rst $m_interconnect_cell/ARESETN
    ##     ad_connect $p_clk $m_interconnect_cell/ACLK
    ##     ad_connect $m_interconnect_cell/M00_AXI $p_name_int
    ##     if {$p_intf_clock ne ""} {
    ##       ad_connect $p_clk $p_intf_clock
    ##     }
    ##   } else {
    ## 
    ##     set_property CONFIG.NUM_SI $m_interconnect_index $m_interconnect_cell
    ##     set clk_index [lsearch [get_bd_nets -of_object [get_bd_pins $m_interconnect_cell/ACLK*]] [get_bd_nets $p_clk]]
    ##     if { $clk_index == -1 } {
    ##         incr sys_mem_clk_index
    ##         set_property CONFIG.NUM_CLKS [expr $sys_mem_clk_index +1] $m_interconnect_cell
    ##         ad_connect $p_clk $m_interconnect_cell/ACLK$sys_mem_clk_index
    ##         set asocc_clk_pin  $m_interconnect_cell/ACLK$sys_mem_clk_index
    ##     } else {
    ##       set asocc_clk_pin [lindex [get_bd_pins $m_interconnect_cell/ACLK*] $clk_index]
    ##     }
    ##     ad_connect $m_interconnect_cell/${i_str}_AXI $p_name_int
    ##     if {$p_intf_clock ne ""} {
    ##       ad_connect $p_clk $p_intf_clock
    ##     }
    ## 
    ##     if {$p_sel eq "NOC"} {
    ##       set_property -dict [list CONFIG.CONNECTIONS {MC_0 { read_bw {1720} write_bw {1720} read_avg_burst {4} write_avg_burst {4}} }] [get_bd_intf_pins /axi_noc_0/${i_str}_AXI]
    ##       # Add the new bus as associated to the clock pin, append new if other exists
    ##       set clk_asoc_port [get_property CONFIG.ASSOCIATED_BUSIF [get_bd_pins $asocc_clk_pin]]
    ##       if {$clk_asoc_port != {}} {
    ##        set clk_asoc_port ${clk_asoc_port}:
    ##       }
    ##       set_property -dict [list CONFIG.ASSOCIATED_BUSIF ${clk_asoc_port}${i_str}_AXI] [get_bd_pins $asocc_clk_pin]
    ##     }
    ## 
    ##     set mem_mapped ""
    ##     if {$p_sel eq "MEM"} {
    ##       # Search a DDR segment that is at least 16MB
    ##       set mem_mapped [get_bd_addr_segs -of [get_bd_addr_spaces -of  [get_bd_intf_pins -filter {NAME=~ *DLMB*} -of [get_bd_cells /sys_mb]]] -regexp -filter {NAME=~ ".*ddr.*" && RANGE=~".*0{6}$"}]
    ##     }
    ##     if {$p_sel eq "SIM"} {
    ##       set mem_mapped [get_bd_addr_segs -of [get_bd_addr_spaces -of  [get_bd_intf_pins -filter {NAME=~ *M_AXI*} -of [get_bd_cells /mng_axi_vip]]] -filter {NAME=~ *DDR* || NAME=~ *ddr*}]
    ##     }
    ## 
    ##     if {$mem_mapped eq ""} {
    ##       assign_bd_address $m_addr_seg
    ##     } else {
    ##       assign_bd_address -offset [get_property OFFSET $mem_mapped] \
    ##                         -range  [get_property RANGE $mem_mapped] $m_addr_seg
    ##     }
    ##   }
    ## 
    ##   if {$p_sel eq "SIM"} {set sys_mem_interconnect_index $m_interconnect_index}
    ##   if {$p_sel eq "MEM"} {set sys_mem_interconnect_index $m_interconnect_index}
    ##   if {$p_sel eq "HPC0"} {set sys_hpc0_interconnect_index $m_interconnect_index}
    ##   if {$p_sel eq "HPC1"} {set sys_hpc1_interconnect_index $m_interconnect_index}
    ##   if {$p_sel eq "HP0"} {set sys_hp0_interconnect_index $m_interconnect_index}
    ##   if {$p_sel eq "HP1"} {set sys_hp1_interconnect_index $m_interconnect_index}
    ##   if {$p_sel eq "HP2"} {set sys_hp2_interconnect_index $m_interconnect_index}
    ##   if {$p_sel eq "HP3"} {set sys_hp3_interconnect_index $m_interconnect_index}
    ## 
    ## }
    ## proc ad_cpu_interconnect {p_address p_name {p_intf_name {}}} {
    ## 
    ##   global sys_zynq
    ##   global sys_cpu_interconnect_index
    ## 
    ##   set i_str "M$sys_cpu_interconnect_index"
    ##   if {$sys_cpu_interconnect_index < 10} {
    ##     set i_str "M0$sys_cpu_interconnect_index"
    ##   }
    ## 
    ##   set use_smart_connect 1
    ##   # SmartConnect has higher resource utilization and worse timing closure on older families
    ##   if {$sys_zynq == 1} {
    ##     set use_smart_connect 0
    ##   }
    ## 
    ##   if {$sys_cpu_interconnect_index == 0} {
    ## 
    ##     if {$use_smart_connect == 1} {
    ##       ad_ip_instance smartconnect axi_cpu_interconnect [ list \
    ##         NUM_MI 1 \
    ##         NUM_SI 1 \
    ##       ]
    ##       ad_connect sys_cpu_clk axi_cpu_interconnect/aclk
    ##       ad_connect sys_cpu_resetn axi_cpu_interconnect/aresetn
    ##     } else {
    ##       ad_ip_instance axi_interconnect axi_cpu_interconnect
    ##       ad_connect sys_cpu_clk axi_cpu_interconnect/ACLK
    ##       ad_connect sys_cpu_clk axi_cpu_interconnect/S00_ACLK
    ##       ad_connect sys_cpu_resetn axi_cpu_interconnect/ARESETN
    ##       ad_connect sys_cpu_resetn axi_cpu_interconnect/S00_ARESETN
    ##     }
    ## 
    ##     if {$sys_zynq == 3} {
    ##       ad_connect sys_cpu_clk sys_cips/m_axi_fpd_aclk
    ##       ad_connect axi_cpu_interconnect/S00_AXI sys_cips/M_AXI_FPD
    ##     }
    ##     if {$sys_zynq == 2} {
    ##       ad_connect sys_cpu_clk sys_ps8/maxihpm0_lpd_aclk
    ##       ad_connect axi_cpu_interconnect/S00_AXI sys_ps8/M_AXI_HPM0_LPD
    ##     }
    ##     if {$sys_zynq == 1} {
    ##       ad_connect sys_cpu_clk sys_ps7/M_AXI_GP0_ACLK
    ##       ad_connect axi_cpu_interconnect/S00_AXI sys_ps7/M_AXI_GP0
    ##     }
    ##     if {$sys_zynq == 0} {
    ##       ad_connect axi_cpu_interconnect/S00_AXI sys_mb/M_AXI_DP
    ##     }
    ##     if {$sys_zynq == -1} {
    ##       ad_connect axi_cpu_interconnect/S00_AXI mng_axi_vip/M_AXI
    ##     }
    ##   }
    ## 
    ##   if {$sys_zynq == 3} {
    ##     set sys_addr_cntrl_space [get_bd_addr_spaces /sys_cips/M_AXI_FPD]
    ##   }
    ##   if {$sys_zynq == 2} {
    ##     set sys_addr_cntrl_space [get_bd_addr_spaces sys_ps8/Data]
    ##   }
    ##   if {$sys_zynq == 1} {
    ##     set sys_addr_cntrl_space [get_bd_addr_spaces sys_ps7/Data]
    ##   }
    ##   if {$sys_zynq == 0} {
    ##     set sys_addr_cntrl_space [get_bd_addr_spaces sys_mb/Data]
    ##   }
    ##   if {$sys_zynq == -1} {
    ##     set sys_addr_cntrl_space [get_bd_addr_spaces mng_axi_vip/Master_AXI]
    ##   }
    ## 
    ##   set sys_cpu_interconnect_index [expr $sys_cpu_interconnect_index + 1]
    ## 
    ## 
    ##   set p_cell [get_bd_cells $p_name]
    ##   set p_intf [get_bd_intf_pins -filter \
    ##     "MODE == Slave && VLNV == xilinx.com:interface:aximm_rtl:1.0 && NAME =~ *$p_intf_name*"\
    ##     -of_objects $p_cell]
    ## 
    ##   set p_hier_cell $p_cell
    ##   set p_hier_intf $p_intf
    ## 
    ##   while {$p_hier_intf != "" && [get_property TYPE $p_hier_cell] == "hier"} {
    ##     set p_hier_intf [find_bd_objs -boundary_type lower \
    ##       -relation connected_to $p_hier_intf]
    ##     if {$p_hier_intf != {}} {
    ##       set p_hier_cell [get_bd_cells -of_objects $p_hier_intf]
    ##     } else {
    ##       set p_hier_cell {}
    ##     }
    ##   }
    ## 
    ##   set p_intf_clock ""
    ##   set p_intf_reset ""
    ## 
    ##   if {$p_hier_cell != {}} {
    ##     set p_intf_name [lrange [split $p_hier_intf "/"] end end]
    ## 
    ##     set p_intf_clock [get_bd_pins -filter "TYPE == clk && \
    ##       (CONFIG.ASSOCIATED_BUSIF == ${p_intf_name} || \
    ##       CONFIG.ASSOCIATED_BUSIF =~ ${p_intf_name}:* || \
    ##       CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name} || \
    ##       CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name}:*)" \
    ##       -quiet -of_objects $p_hier_cell]
    ##     set p_intf_reset [get_bd_pins -filter "TYPE == rst && \
    ##       (CONFIG.ASSOCIATED_BUSIF == ${p_intf_name} || \
    ##        CONFIG.ASSOCIATED_BUSIF =~ ${p_intf_name}:* ||
    ##        CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name} || \
    ##        CONFIG.ASSOCIATED_BUSIF =~ *:${p_intf_name}:*)" \
    ##        -quiet -of_objects $p_hier_cell]
    ## 
    ##     if {($p_intf_clock ne "") && ($p_intf_reset eq "")} {
    ##       set p_intf_reset [get_property CONFIG.ASSOCIATED_RESET [get_bd_pins ${p_intf_clock}]]
    ##       if {$p_intf_reset ne ""} {
    ##         set p_intf_reset [get_bd_pins -filter "NAME == $p_intf_reset" -of_objects $p_hier_cell]
    ##       }
    ##     }
    ## 
    ##     # Trace back up
    ##     set p_hier_cell2 $p_hier_cell
    ## 
    ##     while {$p_intf_clock != {} && $p_hier_cell2 != $p_cell && $p_hier_cell2 != {}} {
    ##       puts $p_intf_clock
    ##       puts $p_hier_cell2
    ##       set p_intf_clock [find_bd_objs -boundary_type upper \
    ##         -relation connected_to $p_intf_clock]
    ##       if {$p_intf_clock != {}} {
    ##         set p_intf_clock [get_bd_pins [get_property PATH $p_intf_clock]]
    ##         set p_hier_cell2 [get_bd_cells -of_objects $p_intf_clock]
    ##       }
    ##     }
    ## 
    ##     set p_hier_cell2 $p_hier_cell
    ## 
    ##     while {$p_intf_reset != {} && $p_hier_cell2 != $p_cell && $p_hier_cell2 != {}} {
    ##       set p_intf_reset [find_bd_objs -boundary_type upper \
    ##         -relation connected_to $p_intf_reset]
    ##       if {$p_intf_reset != {}} {
    ##         set p_intf_reset [get_bd_pins [get_property PATH $p_intf_reset]]
    ##         set p_hier_cell2 [get_bd_cells -of_objects $p_intf_reset]
    ##       }
    ##     }
    ##   }
    ## 
    ## 
    ##   if {[find_bd_objs -quiet -relation connected_to $p_intf_clock] ne ""} {
    ##     set p_intf_clock ""
    ##   }
    ##   if {$p_intf_reset ne ""} {
    ##     if {[find_bd_objs -quiet -relation connected_to $p_intf_reset] ne ""} {
    ##       set p_intf_reset ""
    ##     }
    ##   }
    ## 
    ##   set_property CONFIG.NUM_MI $sys_cpu_interconnect_index [get_bd_cells axi_cpu_interconnect]
    ## 
    ##   if {$use_smart_connect == 0} {
    ##     ad_connect sys_cpu_clk axi_cpu_interconnect/${i_str}_ACLK
    ##     ad_connect sys_cpu_resetn axi_cpu_interconnect/${i_str}_ARESETN
    ##   }
    ##   if {$p_intf_clock ne ""} {
    ##     ad_connect sys_cpu_clk ${p_intf_clock}
    ##   }
    ##   if {$p_intf_reset ne ""} {
    ##     ad_connect sys_cpu_resetn ${p_intf_reset}
    ##   }
    ##   ad_connect axi_cpu_interconnect/${i_str}_AXI ${p_intf}
    ## 
    ##   set p_seg [get_bd_addr_segs -of [get_bd_addr_spaces -of [get_bd_intf_pins -filter "NAME=~ *${p_intf_name}*" -of $p_hier_cell]]]
    ##   set p_index 0
    ##   foreach p_seg_name $p_seg {
    ##     if {$p_index == 0} {
    ##       set p_seg_range [get_property range $p_seg_name]
    ##       if {$p_seg_range < 0x1000} {
    ##         set p_seg_range 0x1000
    ##       }
    ##       if {$sys_zynq == 3} {
    ##         if {($p_address >= 0x44000000) && ($p_address <= 0x4fffffff)} {
    ##           # place axi peripherics in A400_0000-AFFF_FFFF range
    ##           set p_address [expr ($p_address + 0x60000000)]
    ##         } elseif {($p_address >= 0x70000000) && ($p_address <= 0x7fffffff)} {
    ##           # place axi peripherics in B000_0000-BFFF_FFFF range
    ##           set p_address [expr ($p_address + 0x40000000)]
    ##         } else {
    ##           error "ERROR: ad_cpu_interconnect : Cannot map ($p_address) to aperture, \
    ##                 Addess out of range 0x4400_0000 - 0X4FFF_FFFF; 0x7000_0000 - 0X7FFF_FFFF !"
    ##         }
    ##       }
    ##       if {$sys_zynq == 2} {
    ##         if {($p_address >= 0x40000000) && ($p_address <= 0x4fffffff)} {
    ##           set p_address [expr ($p_address + 0x40000000)]
    ##         }
    ##         if {($p_address >= 0x70000000) && ($p_address <= 0x7fffffff)} {
    ##           set p_address [expr ($p_address + 0x20000000)]
    ##         }
    ##       }
    ##       create_bd_addr_seg -range $p_seg_range \
    ##         -offset $p_address $sys_addr_cntrl_space \
    ##         $p_seg_name "SEG_data_${p_name}"
    ##     } else {
    ##       assign_bd_address $p_seg_name
    ##     }
    ##     incr p_index
    ##   }
    ## }
    ## proc ad_cpu_interrupt {p_ps_index p_mb_index p_name} {
    ## 
    ##   global sys_zynq
    ## 
    ##   if {$sys_zynq <= 0} {set p_index_int $p_mb_index}
    ##   if {$sys_zynq >= 1} {set p_index_int $p_ps_index}
    ## 
    ##   set p_index [regsub -all {[^0-9]} $p_index_int ""]
    ##   set m_index [expr ($p_index - 8)]
    ## 
    ##   if {$sys_zynq == 3} {
    ##    if {$p_index < 0 || $p_index > 15} {
    ##       error "ERROR: ad_cpu_interrupt : Interrupt index ($p_index) out of range 0-15 "
    ##     }
    ##     ad_connect $p_name sys_cips/pl_ps_irq$p_index
    ##   }
    ## 
    ##   if {($sys_zynq == 2) && ($p_index <= 7)} {
    ##     set p_net [get_bd_nets -of_objects [get_bd_pins sys_concat_intc_0/In$p_index]]
    ##     set p_pin [get_bd_pins sys_concat_intc_0/In$p_index]
    ## 
    ##     puts "disconnect_bd_net $p_net $p_pin"
    ##     disconnect_bd_net $p_net $p_pin
    ##     ad_connect sys_concat_intc_0/In$p_index $p_name
    ##   }
    ## 
    ##   if {($sys_zynq == 2) && ($p_index >= 8)} {
    ##     set p_net [get_bd_nets -of_objects [get_bd_pins sys_concat_intc_1/In$m_index]]
    ##     set p_pin [get_bd_pins sys_concat_intc_1/In$m_index]
    ## 
    ##     puts "disconnect_bd_net $p_net $p_pin"
    ##     disconnect_bd_net $p_net $p_pin
    ##     ad_connect sys_concat_intc_1/In$m_index $p_name
    ##   }
    ## 
    ##   if {$sys_zynq <= 1} {
    ## 
    ##     set p_net [get_bd_nets -of_objects [get_bd_pins sys_concat_intc/In$p_index]]
    ##     set p_pin [get_bd_pins sys_concat_intc/In$p_index]
    ## 
    ##     puts "disconnect_bd_net $p_net $p_pin"
    ##     disconnect_bd_net $p_net $p_pin
    ##     ad_connect sys_concat_intc/In$p_index $p_name
    ##   }
    ## }
    # if {$argc < 1} {
    #   puts "Expecting at least one argument that specifies the test configuration"
    #   exit 1
    # } else {
    #   set cfg_file [lindex $argv 0]
    # }
    # source "cfgs/${cfg_file}"
    ## global ad_project_params
    # set project_name [file rootname $cfg_file]
    # adi_sim_project_xilinx $project_name "xczu9eg-ffvb1156-2-e"
    WARNING: [Device 21-436] No parts matched 'xczu9eg-ffvb1156-2-e'
    ERROR: [Coretcl 2-106] Specified part could not be found.
    INFO: [Common 17-206] Exiting Vivado at Tue Apr 16 15:02:14 2024...
    

Top Replies

  • Hi  ,

    Looking at the error you got there means that when the testbench is trying to build the project, it is looking for the xczu9eg-ffvb1156-2 part, which is probably not installed on your PC. 

    I see…

  •   
    Leveraging this post, I recently purchased the fmcomms2 board and while I'm waiting for it to arrive, I'm taking the opportunity to study it in detail. I believe that using the testbench would…

    •  Analog Employees 
    in reply to felipeffn +1 verified

    Hi  ,

    I checked out CI builds, which is automated testing, and the fmcomms2 project fails there as well with the main branch of HDL and main branch of Testbenches. Recently there was an update for…

  • Hi  ,

    Looking at the error you got there means that when the testbench is trying to build the project, it is looking for the xczu9eg-ffvb1156-2 part, which is probably not installed on your PC. 

    I see that you already managed to build the project for the Zedboard, so there is a way to make this work. 

    I tried to replicate what you have, and I'm facing some other issues, that come from us. Since the 2022.2 branches from HDL and Testbenches were are not aligned and tested when the releases were created, these 2 cannot be run together. However, there is a workaround for this if you want to check how the testbench works.

    I checked the difference between the main branch and the hdl_2022_r2 on the HDL repository for the project, and the main difference is that it has the Scatter-Gather mode enabled for the DMA core. I don't know how this will affect you, but keep this in mind. On the testbench side, there were some general updates that affect more projects, improvements and fixes mainly.

    Please check out the main branch for both HDL and Testbenches first. In the testbench fmcomms2 folder, you'll find system_project.tcl script, which has a couple of basic stuff in it. What we're looking at here is the adi_sim_project_xilinx $project_name "xcvu9p-flga2104-2L-e". This sets the FPGA part for the simulation. In order to make this work for you you can change the name between the double quotes (") to the Zedboard part, which is: xc7z020clg484-1

    Use this command to prevent error generation from Vivado: export ADI_IGNORE_VERSION_CHECK=1. This will enable you to run the code with older Vivado versions. 

    I tried to build this project using Vivado 2022.2, HDL branch: main, Testbenches branch: main, and it works on my side. 

    If you're still facing issues with the testbenches, let us know.

    Regards,
    -Istvan

  •   
    Thank you very much for your feedback and information, they were extremely valuable. Thank you for explaining the difference between the branches.

    I did what you recommended and initially moved past the previous error, but now I have encountered another error, the reason for which was not very clear. I am attaching the log. 

    I noticed that according to the error in the log, it seems to reference the project 'xc7vx485tffg1157-1' instead of 'xc7z020clg484-1', as previously edited in the system_project.tcl file. Once again, thank you very much for your attention. 

    $: make
    Running test_program test on cfg1 env [~/hdl/testbenches/fmcomms2/runs/cfg1/test_program.log] ...
    Run test_program test on cfg1 env [~/hdl/testbenches/fmcomms2/runs/cfg1/test_program.log] FAILED
    For details see ~/hdl/testbenches/fmcomms2/runs/cfg1/test_program.log


    ****** Vivado v2022.2 (64-bit)
      **** SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
      **** IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
        ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    
    start_gui
    INFO: [Common 17-206] Exiting Vivado at Wed Apr 17 11:21:36 2024...
    
    ****** Vivado v2022.2 (64-bit)
      **** SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
      **** IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
        ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    
    source /mnt/minha_particao/github/hdl/testbenches/scripts/run_sim.tcl
    # set script_path [ file dirname [ file normalize [ info script ] ] ]
    # source $script_path/adi_sim.tcl
    ## variable adi_sim_defines {}
    ## variable design_name "test_harness"
    ## proc adi_sim_add_define {value} {
    ##   global adi_sim_defines
    ##   lappend adi_sim_defines $value
    ## }
    ## proc adi_sim_project_xilinx {project_name {part "xc7vx485tffg1157-1"}} {
    ##   global design_name
    ##   global ad_project_params
    ##   global use_smartconnect
    ## 
    ##   # Create project
    ##   create_project ${project_name} ./runs/${project_name} -part $part -force
    ## 
    ##   # Set project properties
    ##   set_property -name "default_lib" -value "xil_defaultlib" -objects [current_project]
    ## 
    ##   # Set IP repository paths
    ##   set_property "ip_repo_paths" "[file normalize "./../../library"] " \
    ##     [get_filesets sources_1]
    ## 
    ##   # Rebuild user ip_repo's index before adding any source files
    ##   update_ip_catalog -rebuild
    ## 
    ##   ## Create the bd
    ##   ######################
    ##   create_bd_design $design_name
    ## 
    ##   global sys_zynq
    ##   set sys_zynq -1
    ##   if { ![info exists ad_project_params(CUSTOM_HARNESS)] || !$ad_project_params(CUSTOM_HARNESS) } {
    ##     source ../common/test_harness/test_harness_system_bd.tcl
    ##   }
    ## 
    ##   # transfer tcl parameters as defines to verilog
    ##   foreach {k v} [array get ad_project_params] {
    ##     if { [llength $ad_project_params($k)] == 1} {
    ##       adi_sim_add_define $k=$v
    ##     } else {
    ##       foreach {h v} $ad_project_params($k) {
    ##         adi_sim_add_define ${k}_${h}=$v
    ##       }
    ##     }
    ##   }
    ## 
    ##   # write tcl parameters into a file
    ##   set outfile [open "./runs/${project_name}/parameters.log" w+]
    ##   puts $outfile "Configuration parameters\n"
    ##   foreach name [array names ad_project_params] {
    ##     if { [llength $ad_project_params($name)] == 1} {
    ##       puts $outfile "$name : $ad_project_params($name)"
    ##     } else {
    ##       puts $outfile "$name :"
    ##       foreach {k v} $ad_project_params($name) {
    ##         puts $outfile "  $k : $v"
    ##       }
    ##     }
    ##   }
    ##   close $outfile
    ## 
    ##   # Build the test harness based on the topology
    ##   source system_bd.tcl
    ## 
    ##   save_bd_design
    ##   validate_bd_design
    ## 
    ##   # Pass the test harness instance name to the simulation
    ##   adi_sim_add_define "TH=$design_name"
    ## 
    ##   # Use a define for the top module
    ##   adi_sim_add_define "TB=system_tb"
    ## }
    ## proc adi_sim_project_files {project_files} {
    ##   add_files -fileset sim_1 $project_files
    ##   # Set 'sim_1' fileset properties
    ##   set_property -name "top" -value "system_tb" -objects [get_filesets sim_1]
    ## }
    ## proc adi_sim_generate {project_name } {
    ##   global design_name
    ##   global adi_sim_defines
    ## 
    ##   # Set the defines for simulation
    ##   set_property verilog_define $adi_sim_defines [get_filesets sim_1]
    ## 
    ##   set_property -name {xsim.simulate.runtime} -value {} -objects [get_filesets sim_1]
    ## 
    ##   # Show all Xilinx primitives e.g GTYE4_COMMON
    ##   set_property -name {xsim.elaborate.debug_level} -value {all} -objects [get_filesets sim_1]
    ##   # Log all waves
    ##   set_property -name {xsim.simulate.log_all_signals} -value {true} -objects [get_filesets sim_1]
    ## 
    ##   set_property -name {xsim.simulate.xsim.more_options} -value {-sv_seed random} -objects [get_filesets sim_1]
    ## 
    ##   set project_system_dir "./runs/$project_name/$project_name.srcs/sources_1/bd/$design_name"
    ## 
    ##   generate_target Simulation [get_files $project_system_dir/$design_name.bd]
    ## 
    ##   set_property include_dirs . [get_filesets sim_1]
    ## 
    ##   set_msg_config -string mb_reset -suppress
    ## }
    ## proc adi_open_project {project_path} {
    ##   open_project $project_path
    ## }
    ## proc adi_update_define {name value} {
    ##   set defines [get_property verilog_define [get_filesets sim_1]]
    ##   set defines_new {}
    ##   foreach def $defines {
    ##     set def [split $def {=}]
    ##     if {[lindex $def 0] == $name} {
    ##       set def [lreplace $def 1 1 $value]
    ##       puts "reaplacing"
    ##       }
    ##     lappend defines_new "[lindex $def 0]=[lindex $def 1]"
    ##   }
    ##   set_property verilog_define $defines_new [get_filesets sim_1]
    ## 
    ## }
    ## proc adi_project_files {project_files} {
    ## 
    ##   foreach pfile $project_files {
    ##     if {[string range $pfile [expr 1 + [string last . $pfile]] end] == "xdc"} {
    ##       add_files -norecurse -fileset constrs_1 $pfile
    ##     } else {
    ##       add_files -norecurse -fileset sources_1 $pfile
    ##     }
    ##   }
    ## }
    # if {$argc < 3} {
    #   puts "Expecting at least one argument that specifies the test configuration and procedure"
    #   exit 1
    # } else {
    #   set topology_file [lindex $argv 0]
    #   set test_program [lindex $argv 1]
    #   set mode [lindex $argv 2]
    # }
    # set project_name [file rootname $topology_file]
    # adi_open_project "runs/$project_name/$project_name.xpr"
    Scanning sources...
    Finished scanning sources
    INFO: [IP_Flow 19-234] Refreshing IP repositories
    INFO: [IP_Flow 19-1700] Loaded user IP repository '/mnt/minha_particao/github/hdl/library'.
    INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/felipe/Xilinx_2022_2/Vivado/2022.2/data/ip'.
    open_project: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1318.449 ; gain = 0.023 ; free physical = 6614 ; free virtual = 13818
    # adi_update_define TEST_PROGRAM $test_program
    reaplacing
    # launch_simulation
    Command: launch_simulation 
    INFO: [Vivado 12-12493] Simulation top is 'system_tb'
    WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
    INFO: [Vivado 12-5682] Launching behavioral simulation in '/mnt/minha_particao/github/hdl/testbenches/fmcomms2/runs/cfg1/cfg1.sim/sim_1/behav/xsim'
    INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
    INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
    INFO: [SIM-utils-51] Simulation object is 'sim_1'
    INFO: [SIM-utils-72] Using boost library from '/home/felipe/Xilinx_2022_2/Vivado/2022.2/tps/boost_1_72_0'
    INFO: [USF-XSim-7] Finding pre-compiled libraries...
    INFO: [USF-XSim-11] File '/home/felipe/Xilinx_2022_2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/mnt/minha_particao/github/hdl/testbenches/fmcomms2/runs/cfg1/cfg1.sim/sim_1/behav/xsim'
    INFO: [SIM-utils-54] Inspecting design source files for 'system_tb' in fileset 'sim_1'...
    INFO: [SIM-utils-43] Exported '/mnt/minha_particao/github/hdl/testbenches/fmcomms2/runs/cfg1/cfg1.sim/sim_1/behav/xsim/sc_xtlm_test_harness_axi_cpu_interconnect_0.mem'
    INFO: [SIM-utils-43] Exported '/mnt/minha_particao/github/hdl/testbenches/fmcomms2/runs/cfg1/cfg1.sim/sim_1/behav/xsim/sc_xtlm_test_harness_axi_mem_interconnect_0.mem'
    INFO: [USF-XSim-97] Finding global include files...
    INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
    INFO: [USF-XSim-2] XSim::Compile design
    INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/mnt/minha_particao/github/hdl/testbenches/fmcomms2/runs/cfg1/cfg1.sim/sim_1/behav/xsim'
    xvlog --incr --relax -L uvm -L axi_vip_v1_1_13 -L smartconnect_v1_0 -L clk_vip_v1_0_2 -L rst_vip_v1_0_4 -L xilinx_vip -prj system_tb_vlog.prj
    xvhdl --incr --relax -prj system_tb_vhdl.prj
    Waiting for jobs to finish...
    No pending jobs, compilation finished.
    INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
    INFO: [USF-XSim-3] XSim::Elaborate design
    INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/mnt/minha_particao/github/hdl/testbenches/fmcomms2/runs/cfg1/cfg1.sim/sim_1/behav/xsim'
    xelab --incr --debug all --relax --mt 8 -d MNG_AXI=mng_axi_vip -d DDR_AXI=ddr_axi_vip -d SYS_CLK=sys_clk_vip -d DMA_CLK=dma_clk_vip -d DDR_CLK=ddr_clk_vip -d SYS_RST=sys_rst_vip -d DDR_BA=2147483648 -d SSI_CLK=ssi_clk_vip -d RX_DMA_BA=2084569088 -d TX_DMA_BA=2084700160 -d AXI_AD9361_BA=2030174208 -d TH=test_harness -d TB=system_tb -d TEST_PROGRAM=test_program -L xil_defaultlib -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_13 -L axi_lite_ipif_v3_0_4 -L axi_intc_v4_1_17 -L xlconcat_v2_1_4 -L clk_vip_v1_0_2 -L rst_vip_v1_0_4 -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L xlconstant_v1_1_7 -L smartconnect_v1_0 -L axi_register_slice_v2_1_27 -L util_reduced_logic_v2_0_4 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot system_tb_behav xil_defaultlib.system_tb xil_defaultlib.glbl -log elaborate.log
    Vivado Simulator v2022.2
    Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
    Running: /home/felipe/Xilinx_2022_2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug all --relax --mt 8 -d MNG_AXI=mng_axi_vip -d DDR_AXI=ddr_axi_vip -d SYS_CLK=sys_clk_vip -d DMA_CLK=dma_clk_vip -d DDR_CLK=ddr_clk_vip -d SYS_RST=sys_rst_vip -d DDR_BA=2147483648 -d SSI_CLK=ssi_clk_vip -d RX_DMA_BA=2084569088 -d TX_DMA_BA=2084700160 -d AXI_AD9361_BA=2030174208 -d TH=test_harness -d TB=system_tb -d TEST_PROGRAM=test_program -L xil_defaultlib -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_13 -L axi_lite_ipif_v3_0_4 -L axi_intc_v4_1_17 -L xlconcat_v2_1_4 -L clk_vip_v1_0_2 -L rst_vip_v1_0_4 -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L xlconstant_v1_1_7 -L smartconnect_v1_0 -L axi_register_slice_v2_1_27 -L util_reduced_logic_v2_0_4 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot system_tb_behav xil_defaultlib.system_tb xil_defaultlib.glbl -log elaborate.log 
    Using 8 slave threads.
    Starting static elaboration
    Pass Through NonSizing Optimizer
    ERROR: [VRFC 10-2063] Module <test_program> not found while processing module instance <test> [/mnt/minha_particao/github/hdl/testbenches/fmcomms2/system_tb.sv:45]
    ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.
    INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
    INFO: [USF-XSim-99] Step results log file:'/mnt/minha_particao/github/hdl/testbenches/fmcomms2/runs/cfg1/cfg1.sim/sim_1/behav/xsim/elaborate.log'
    ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or '/mnt/minha_particao/github/hdl/testbenches/fmcomms2/runs/cfg1/cfg1.sim/sim_1/behav/xsim/elaborate.log' file for more information.
    ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
    launch_simulation: Time (s): cpu = 00:00:09 ; elapsed = 00:00:09 . Memory (MB): peak = 1590.582 ; gain = 272.133 ; free physical = 6605 ; free virtual = 13789
    ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
    
        while executing
    "launch_simulation"
        (file "/mnt/minha_particao/github/hdl/testbenches/scripts/run_sim.tcl" line 21)
    INFO: [Common 17-206] Exiting Vivado at Wed Apr 17 11:22:05 2024...
    
    ****** Vivado v2022.2 (64-bit)
      **** SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
      **** IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
        ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    
    source /mnt/minha_particao/github/hdl/testbenches/scripts/run_sim.tcl
    # set script_path [ file dirname [ file normalize [ info script ] ] ]
    # source $script_path/adi_sim.tcl
    ## variable adi_sim_defines {}
    ## variable design_name "test_harness"
    ## proc adi_sim_add_define {value} {
    ##   global adi_sim_defines
    ##   lappend adi_sim_defines $value
    ## }
    ## proc adi_sim_project_xilinx {project_name {part "xc7vx485tffg1157-1"}} {
    ##   global design_name
    ##   global ad_project_params
    ##   global use_smartconnect
    ## 
    ##   # Create project
    ##   create_project ${project_name} ./runs/${project_name} -part $part -force
    ## 
    ##   # Set project properties
    ##   set_property -name "default_lib" -value "xil_defaultlib" -objects [current_project]
    ## 
    ##   # Set IP repository paths
    ##   set_property "ip_repo_paths" "[file normalize "./../../library"] " \
    ##     [get_filesets sources_1]
    ## 
    ##   # Rebuild user ip_repo's index before adding any source files
    ##   update_ip_catalog -rebuild
    ## 
    ##   ## Create the bd
    ##   ######################
    ##   create_bd_design $design_name
    ## 
    ##   global sys_zynq
    ##   set sys_zynq -1
    ##   if { ![info exists ad_project_params(CUSTOM_HARNESS)] || !$ad_project_params(CUSTOM_HARNESS) } {
    ##     source ../common/test_harness/test_harness_system_bd.tcl
    ##   }
    ## 
    ##   # transfer tcl parameters as defines to verilog
    ##   foreach {k v} [array get ad_project_params] {
    ##     if { [llength $ad_project_params($k)] == 1} {
    ##       adi_sim_add_define $k=$v
    ##     } else {
    ##       foreach {h v} $ad_project_params($k) {
    ##         adi_sim_add_define ${k}_${h}=$v
    ##       }
    ##     }
    ##   }
    ## 
    ##   # write tcl parameters into a file
    ##   set outfile [open "./runs/${project_name}/parameters.log" w+]
    ##   puts $outfile "Configuration parameters\n"
    ##   foreach name [array names ad_project_params] {
    ##     if { [llength $ad_project_params($name)] == 1} {
    ##       puts $outfile "$name : $ad_project_params($name)"
    ##     } else {
    ##       puts $outfile "$name :"
    ##       foreach {k v} $ad_project_params($name) {
    ##         puts $outfile "  $k : $v"
    ##       }
    ##     }
    ##   }
    ##   close $outfile
    ## 
    ##   # Build the test harness based on the topology
    ##   source system_bd.tcl
    ## 
    ##   save_bd_design
    ##   validate_bd_design
    ## 
    ##   # Pass the test harness instance name to the simulation
    ##   adi_sim_add_define "TH=$design_name"
    ## 
    ##   # Use a define for the top module
    ##   adi_sim_add_define "TB=system_tb"
    ## }
    ## proc adi_sim_project_files {project_files} {
    ##   add_files -fileset sim_1 $project_files
    ##   # Set 'sim_1' fileset properties
    ##   set_property -name "top" -value "system_tb" -objects [get_filesets sim_1]
    ## }
    ## proc adi_sim_generate {project_name } {
    ##   global design_name
    ##   global adi_sim_defines
    ## 
    ##   # Set the defines for simulation
    ##   set_property verilog_define $adi_sim_defines [get_filesets sim_1]
    ## 
    ##   set_property -name {xsim.simulate.runtime} -value {} -objects [get_filesets sim_1]
    ## 
    ##   # Show all Xilinx primitives e.g GTYE4_COMMON
    ##   set_property -name {xsim.elaborate.debug_level} -value {all} -objects [get_filesets sim_1]
    ##   # Log all waves
    ##   set_property -name {xsim.simulate.log_all_signals} -value {true} -objects [get_filesets sim_1]
    ## 
    ##   set_property -name {xsim.simulate.xsim.more_options} -value {-sv_seed random} -objects [get_filesets sim_1]
    ## 
    ##   set project_system_dir "./runs/$project_name/$project_name.srcs/sources_1/bd/$design_name"
    ## 
    ##   generate_target Simulation [get_files $project_system_dir/$design_name.bd]
    ## 
    ##   set_property include_dirs . [get_filesets sim_1]
    ## 
    ##   set_msg_config -string mb_reset -suppress
    ## }
    ## proc adi_open_project {project_path} {
    ##   open_project $project_path
    ## }
    ## proc adi_update_define {name value} {
    ##   set defines [get_property verilog_define [get_filesets sim_1]]
    ##   set defines_new {}
    ##   foreach def $defines {
    ##     set def [split $def {=}]
    ##     if {[lindex $def 0] == $name} {
    ##       set def [lreplace $def 1 1 $value]
    ##       puts "reaplacing"
    ##       }
    ##     lappend defines_new "[lindex $def 0]=[lindex $def 1]"
    ##   }
    ##   set_property verilog_define $defines_new [get_filesets sim_1]
    ## 
    ## }
    ## proc adi_project_files {project_files} {
    ## 
    ##   foreach pfile $project_files {
    ##     if {[string range $pfile [expr 1 + [string last . $pfile]] end] == "xdc"} {
    ##       add_files -norecurse -fileset constrs_1 $pfile
    ##     } else {
    ##       add_files -norecurse -fileset sources_1 $pfile
    ##     }
    ##   }
    ## }
    # if {$argc < 3} {
    #   puts "Expecting at least one argument that specifies the test configuration and procedure"
    #   exit 1
    # } else {
    #   set topology_file [lindex $argv 0]
    #   set test_program [lindex $argv 1]
    #   set mode [lindex $argv 2]
    # }
    # set project_name [file rootname $topology_file]
    # adi_open_project "runs/$project_name/$project_name.xpr"
    Scanning sources...
    Finished scanning sources
    INFO: [IP_Flow 19-234] Refreshing IP repositories
    INFO: [IP_Flow 19-1700] Loaded user IP repository '/mnt/minha_particao/github/hdl/library'.
    INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/felipe/Xilinx_2022_2/Vivado/2022.2/data/ip'.
    open_project: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1283.078 ; gain = 25.109 ; free physical = 4837 ; free virtual = 12268
    # adi_update_define TEST_PROGRAM $test_program
    reaplacing
    # launch_simulation
    Command: launch_simulation 
    INFO: [Vivado 12-12493] Simulation top is 'system_tb'
    WARNING: [Vivado 12-13277] Compiled library path does not exist: ''
    INFO: [Vivado 12-5682] Launching behavioral simulation in '/mnt/minha_particao/github/hdl/testbenches/fmcomms2/runs/cfg1/cfg1.sim/sim_1/behav/xsim'
    INFO: [Vivado 12-13660] Precompiled IP simulation library mode is enabled (default). The design IP libraries will be referenced from the compiled library path. Please note that if the precompiled version of the library is not found from the path or the IP is in locked state, then the library source files for these IPs will be compiled locally as part of the compile order.
    INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
    INFO: [SIM-utils-51] Simulation object is 'sim_1'
    INFO: [SIM-utils-72] Using boost library from '/home/felipe/Xilinx_2022_2/Vivado/2022.2/tps/boost_1_72_0'
    INFO: [USF-XSim-7] Finding pre-compiled libraries...
    INFO: [USF-XSim-11] File '/home/felipe/Xilinx_2022_2/Vivado/2022.2/data/xsim/xsim.ini' copied to run dir:'/mnt/minha_particao/github/hdl/testbenches/fmcomms2/runs/cfg1/cfg1.sim/sim_1/behav/xsim'
    INFO: [SIM-utils-54] Inspecting design source files for 'system_tb' in fileset 'sim_1'...
    INFO: [SIM-utils-43] Exported '/mnt/minha_particao/github/hdl/testbenches/fmcomms2/runs/cfg1/cfg1.sim/sim_1/behav/xsim/sc_xtlm_test_harness_axi_cpu_interconnect_0.mem'
    INFO: [SIM-utils-43] Exported '/mnt/minha_particao/github/hdl/testbenches/fmcomms2/runs/cfg1/cfg1.sim/sim_1/behav/xsim/sc_xtlm_test_harness_axi_mem_interconnect_0.mem'
    INFO: [USF-XSim-97] Finding global include files...
    INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
    INFO: [USF-XSim-2] XSim::Compile design
    INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in '/mnt/minha_particao/github/hdl/testbenches/fmcomms2/runs/cfg1/cfg1.sim/sim_1/behav/xsim'
    xvlog --incr --relax -L uvm -L axi_vip_v1_1_13 -L smartconnect_v1_0 -L clk_vip_v1_0_2 -L rst_vip_v1_0_4 -L xilinx_vip -prj system_tb_vlog.prj
    xvhdl --incr --relax -prj system_tb_vhdl.prj
    Waiting for jobs to finish...
    No pending jobs, compilation finished.
    INFO: [USF-XSim-69] 'compile' step finished in '2' seconds
    INFO: [USF-XSim-3] XSim::Elaborate design
    INFO: [USF-XSim-61] Executing 'ELABORATE' step in '/mnt/minha_particao/github/hdl/testbenches/fmcomms2/runs/cfg1/cfg1.sim/sim_1/behav/xsim'
    xelab --incr --debug all --relax --mt 8 -d MNG_AXI=mng_axi_vip -d DDR_AXI=ddr_axi_vip -d SYS_CLK=sys_clk_vip -d DMA_CLK=dma_clk_vip -d DDR_CLK=ddr_clk_vip -d SYS_RST=sys_rst_vip -d DDR_BA=2147483648 -d SSI_CLK=ssi_clk_vip -d RX_DMA_BA=2084569088 -d TX_DMA_BA=2084700160 -d AXI_AD9361_BA=2030174208 -d TH=test_harness -d TB=system_tb -d TEST_PROGRAM=test_program -L xil_defaultlib -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_13 -L axi_lite_ipif_v3_0_4 -L axi_intc_v4_1_17 -L xlconcat_v2_1_4 -L clk_vip_v1_0_2 -L rst_vip_v1_0_4 -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L xlconstant_v1_1_7 -L smartconnect_v1_0 -L axi_register_slice_v2_1_27 -L util_reduced_logic_v2_0_4 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot system_tb_behav xil_defaultlib.system_tb xil_defaultlib.glbl -log elaborate.log
    Vivado Simulator v2022.2
    Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
    Running: /home/felipe/Xilinx_2022_2/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug all --relax --mt 8 -d MNG_AXI=mng_axi_vip -d DDR_AXI=ddr_axi_vip -d SYS_CLK=sys_clk_vip -d DMA_CLK=dma_clk_vip -d DDR_CLK=ddr_clk_vip -d SYS_RST=sys_rst_vip -d DDR_BA=2147483648 -d SSI_CLK=ssi_clk_vip -d RX_DMA_BA=2084569088 -d TX_DMA_BA=2084700160 -d AXI_AD9361_BA=2030174208 -d TH=test_harness -d TB=system_tb -d TEST_PROGRAM=test_program -L xil_defaultlib -L axi_infrastructure_v1_1_0 -L axi_vip_v1_1_13 -L axi_lite_ipif_v3_0_4 -L axi_intc_v4_1_17 -L xlconcat_v2_1_4 -L clk_vip_v1_0_2 -L rst_vip_v1_0_4 -L lib_cdc_v1_0_2 -L proc_sys_reset_v5_0_13 -L xlconstant_v1_1_7 -L smartconnect_v1_0 -L axi_register_slice_v2_1_27 -L util_reduced_logic_v2_0_4 -L uvm -L xilinx_vip -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot system_tb_behav xil_defaultlib.system_tb xil_defaultlib.glbl -log elaborate.log 
    Using 8 slave threads.
    Starting static elaboration
    Pass Through NonSizing Optimizer
    ERROR: [VRFC 10-2063] Module <test_program> not found while processing module instance <test> [/mnt/minha_particao/github/hdl/testbenches/fmcomms2/system_tb.sv:45]
    ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.
    INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds
    INFO: [USF-XSim-99] Step results log file:'/mnt/minha_particao/github/hdl/testbenches/fmcomms2/runs/cfg1/cfg1.sim/sim_1/behav/xsim/elaborate.log'
    ERROR: [USF-XSim-62] 'elaborate' step failed with error(s). Please check the Tcl console output or '/mnt/minha_particao/github/hdl/testbenches/fmcomms2/runs/cfg1/cfg1.sim/sim_1/behav/xsim/elaborate.log' file for more information.
    ERROR: [Vivado 12-4473] Detected error while running simulation. Please correct the issue and retry this operation.
    launch_simulation: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1585.961 ; gain = 302.883 ; free physical = 4835 ; free virtual = 12260
    ERROR: [Common 17-39] 'launch_simulation' failed due to earlier errors.
    
        while executing
    "launch_simulation"
        (file "/mnt/minha_particao/github/hdl/testbenches/scripts/run_sim.tcl" line 21)
    INFO: [Common 17-206] Exiting Vivado at Wed Apr 17 11:36:03 2024...
    

  • Hi  ,

    I checked the error message, and it has 2 messages, which suggests to me that the project was not cleaned after it was rerun. I'd like you to clean the fmcomms2 testbench by running this command: make clean all. This will clean and rebuild the entire testbench. 

    I'm requesting this command, since the way our Makefile works is that it checks if something changes for the base files that are listed for the specific testbench. Since the files are not modified, the makefile doesn't rebuild the project, and you might be left with an old, broken project, where the scripts might not work. I'd also recommend that you go into the hdl/libraries folder and run a make clean as well, to make sure that the libraries is cleaned up too. Clean the libraries first, and then run the make clean all in the testbench. The testbench will automatically rebuild the libraries that it needs. 

    Regarding your question on the FPGA part, that seems a bit troublesome. Since you managed to create the project for fmcomms2 already for the Zedboard, I would assume that you have the FPGA board files installed on your PC. But the simulation environment doesn't seem to like it this way, which is weird. Please try to check if you have the necessary board files. Create a new project and at the part selection try and find the FPGA part that the Zedboard is using. I'm confident to say that this will have little to no impact on the testbench, but I'd still look into it, to make sure you'll not going to run into other issues later on. 

    Please let me know if you need assistance with anything. 

    Regards,
    -Istvan

  •   
    Thank you once again for your support. Unfortunately, despite following the recommended steps above, I am still encountering problems =/.

    ERROR: [VRFC 10-2063] Module <test_program> not found while processing module instance <test> [~/testbenches/fmcomms2/system_tb.sv:45]
    ERROR: [XSIM 43-3322] Static elaboration of top level Verilog design unit(s) in library work failed.
    INFO: [USF-XSim-69] 'elaborate' step finished in '1' seconds


    I am attaching the log below.

    5344.test_program.log

  •   
    Leveraging this post, I recently purchased the fmcomms2 board and while I'm waiting for it to arrive, I'm taking the opportunity to study it in detail. I believe that using the testbench would be an excellent way to help me understand it better, especially for any future modifications I might make to the reference design. My goal is to simulate the AD sample data or something similar interacting with the axi_ad 9361 block in the reference design while I wait for the actual board. I think the testbench fundamentals would be essential for this, right? If you have any tips on this, I would also be grateful.

  • Hi  ,

    Regarding the question on what should you do and in what order, depends on what your goal really is. Since you want to understand what is going on in the block design as well as make some edits to it maybe, you'll probably need to dive deep into it. 

    First thing I'd recommend is to build the fmcomms2 project, open the block design in Vivado, and try to understand the different blocks, and their relationship between them. For this, use the https://wiki.analog.com/start where you'll find description of the blocks, what are they meant to do, how do they work, and see how do each of these connect and fit into the big picture.

    Once this is done and you more or less got to the point where the documentation and the block design can't provide the information you seek, then you go to the simulation, and figure out what is going on there. The simulation allows you to access registers and wires that are inside the IP cores, and for this you'll need to look at the IPs source as well. Up until now, we can help.

    From this point onward, you're on your own. Of course, if you have questions regarding certain IPs, their limitations, what we tried, or what you're trying to do, we can take a look at it, and try to figure, if it's something that can/can't/might work. 

    Regards,
    -Istvan

  • Hi  ,

    I checked out CI builds, which is automated testing, and the fmcomms2 project fails there as well with the main branch of HDL and main branch of Testbenches. Recently there was an update for the testbench, and this simulation wasn't tested prior to the merge. I created a branch to fix this, and opened a PR to be reviewed and merged into the main branch. You can check it out and run the simulation, then branch's name is: fmcomms2_fix. This should fix the issue you had previously with the missing test program. Don't forget to check the FPGA part once you pull and check out the new branch. 

    Regards,
    -Istvan

  • Hi  ,

    Did you manage to solve your issue or do you have some other questions?
    Please specify which comment was helpful so that other EngineerZone users that have this issue will have an answer that worked for you. 

    Regards,
    -Istvan

  • Hello,  

    Sorry for the delay in getting back to you; I was traveling. The recommendations worked well, and I confirmed that there was indeed a minor error in the SystemVerilog code. Thank you for your help and insights.