Hi everyone,
I want to port ad9082-fmca-ebz-zc706 2021_R1 design to te0782 z7100 module with custom carrier board we designed and ad9082-fmca-ebz evaluation board. Carrier board connects te0782 and ad9082-fmca-ebz each other.
In my original design, only change i made is to remove tx_dma and tx_data_offload and add sweep generator. I left JESD parameters as is (TX_JESD 9 & RX_JESD 10). My design works on zc706 with no problem. I am using no-OS when initializing ad9082.
When I port the design, right after initialization of ad9082, I am observing random tones on spectrum analyzer. My signal isn't transmitted yet at this point. Black trace shows max hold samples.
I can see my sweep signal at output when I begin transmitting the signal, although these tones still exist.
Hello
tx_adxcvr: OK (10000000 kHz)
ad9081_jesd_rx_link_status_print: JESD TX (JRX) Link1 0x0 lanes in DATA
tx_adxcvr: OK (10000000 kHz)
ad9081_jesd_rx_link_status_print: JESD TX (JRX) Link1 0xF lanes in DATA
ad9081_jesd_tx_link_status_print: JESD RX (JTX) Link1 in CGS, SYNC asserted, PLL locked, PHASE established, MODE valid
DAC IRQ status 0xf043000040
AD9081 Rev. 3 Grade 2 (API 1.2.2) probed
tx_jesd status:
Link is enabled
Measured Link Clock: 249.998 MHz
Reported Link Clock: 250.000 MHz
Lane rate: 10000.000 MHz
Lane rate / 40: 250.000 MHz
LMFC rate: 7.812 MHz
SYNC~: deasserted
Link status: DATA
SYSREF captured: Yes
SYSREF alignment error: No
rx_jesd status:
Link is enabled
Measured Link Clock: 249.994 MHz
Reported Link Clock: 250.000 MHz
Lane rate: 10000.000 MHz
Lane rate / 40: 250.000 MHz
LMFC rate: 7.812 MHz
Link status: CGS
SYSREF captured: Yes
SYSREF alignment error: No
tx_dac: Successfully initialized (250000000 Hz)
rx_adc: Successfully initialized (249998474 Hz)
rx link status was CGS all the time but since my project requires only transmitting, i didn't touch it.
I've checked our custom carrier board and te0782 pins again and i found that
- fpga_refclk_in pins are inverted in te0782. I also realized that they are connected to bank110 instead of bank109 but i think this is not a problem since zynq can get refclk from north and south banks.
- in our custom carrier board, clkin10 pins are connected to clkin0 (CLK2_M2C) pins instead of clkin10 (LA00_CC) pins in FMC. In no-OS, clkin0 is already initialized with the same frequency as clkin10.
- in our carrier board, the order of fpga_serdin pins is different while fpga_serdout pins order is as they should be.
I've tried to swap fpga_refclk_in pins in my reference design but implementation fails this time too.
Probably the problem is the polarity of refclk but is there a way to correct it within FPGA? What else can i look at to find root cause of problem?
Thanks for your help.
