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About the Channel CPACK Utility Core IP output data in the ADRV9009 ZC706 reference design

Category: Software
Product Number: 0
Software Version: 21.2

hello, I have a question about the Channel CPACK Utility Core IP output data in the ADRV9009 ZC706 reference design.I made a testbench about this ip in a new projech,which only contains this ip core.And from the scoped image below(if it's clear enough).I think the output packed_fifo_wr_data seems wrong,unlinke it's wiki introduction,it's seems to be 0000 0000 00000 0000 4444 3333 2222 1111.It is my error?Or it is the right output.My testbench only simply input the data and give a enable signal.

and I also test when 3 channels are enabled.I am not sure it is right or wrong.and it's data is 01030201 02010302 03020103 which every single number means four same numble.

Thanks,

Cai

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  • Hi  ,

    I looked into this issue and created a testbench for the CPack and the UPack instances since these are similar modules. I tested the modules in different forms by eye, and didn't seem to find an issue with them yet. I'll still have to integrate a scoreboard to make sure that all of the data is transmitted properly and everything is aligned as it should be. 

    You can find this testbench here: https://github.com/analogdevicesinc/testbenches/tree/util_pack. It is on a separate repository dedicated to IP and project verification. 

    A quick guide on how to use the testbenches repository, since we're don't have a documentation for it just yet. 
    1: Clone the Testbenches repository inside the HDL repository (HDL will contain Testbenches)
    2: Go to util_pack
    3: Run this command: make MODE=gui (this will build the project, open the Vivado gui and run the simulation as well)
    4: Check the data and other things you're interested in

    Mentions:
    You can change the configuration to whatever you want to test by going to the cfg folder under util_pack and editing the cfg1.txt file. This will give you other options on how you can set up CPack and UPack parameters for the testbench.
    Once you edit the file, you can just rerun make MODE=gui. This will rebuild the project only if the configuration file was modified. Otherwise, it'll just run the simulation. If you want to make sure you rebuild everything from scratch, so nothing is left behind, run make clean all MODE=gui. This will always clear the project and rebuild it. 

    I'll be working on the scoreboard for these modules tomorrow and get back to you with an update. 

    Regards,
    -Istvan

  • Hi Istvan,

    I truly appreciate your timely help.And I'll try the method you provided today.Besides,I check my project again,I still can't find the question out.My project's block design is as follows.

    If you have any suggestions for that or if there some questions I have never noticed?

  • Hi  ,

    Before I suggest anything on this side, I'd like to help you build and open up the testbench project, as it'll help you understand the packers a little better.
    The testbench itself that you'll see is different from what you've created and it's a bit more difficult to understand. It has some extra stuff around it so it's easier to integrate it into other systems for newcomers.
    After you manage to build the project, check out the waveform, we can go further with your issue. 

    Regards,
    -Istvan

Reply
  • Hi  ,

    Before I suggest anything on this side, I'd like to help you build and open up the testbench project, as it'll help you understand the packers a little better.
    The testbench itself that you'll see is different from what you've created and it's a bit more difficult to understand. It has some extra stuff around it so it's easier to integrate it into other systems for newcomers.
    After you manage to build the project, check out the waveform, we can go further with your issue. 

    Regards,
    -Istvan

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