About the Channel CPACK Utility Core IP output data in the ADRV9009 ZC706 reference design

Hi,

We will be looking into this matter next week.

Best regards,
Iulia

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/04/09 11:49:41
// Design Name: 
// Module Name: cpack_sim
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module cpack_sim();
//input
reg clk;
reg reset;
reg enable_0;
reg enable_1;
reg enable_2;
reg enable_3;
reg [3:0] fifo_wr_en;
reg [31:0] fifo_wr_data_0;
reg [31:0] fifo_wr_data_1;
reg [31:0] fifo_wr_data_2;
reg [31:0] fifo_wr_data_3;
reg packed_fifo_wr_overflow;
//output
wire fifo_wr_overflow;
wire packed_fifo_wr_en;
wire packed_fifo_wr_sync;
wire [127:0] packed_fifo_wr_data;

design_1_wrapper u_util_cpack2
(
.enable_0 (enable_0),
.enable_1(enable_1),
.enable_2(enable_2),
.enable_3(enable_3),
.fifo_wr_data_0 (fifo_wr_data_0),
.fifo_wr_data_1 (fifo_wr_data_1),
.fifo_wr_data_2 (fifo_wr_data_2),
.fifo_wr_data_3 (fifo_wr_data_3),
.clk (clk),
.reset (reset),
.packed_fifo_wr_overflow (packed_fifo_wr_overflow),
.packed_fifo_wr_sync(packed_fifo_wr_sync),
.packed_fifo_wr_data (packed_fifo_wr_data),
.fifo_wr_overflow (fifo_wr_overflow),
.packed_fifo_wr_en (packed_fifo_wr_en),
.fifo_wr_en (fifo_wr_en)
);

initial
begin
  clk=1'b0;
  reset=1'b1;
  #200
  reset=1'b0;
  enable_0=1'b1;
  enable_1=1'b1;
  enable_2=1'b1;
  enable_3=1'b0;
  fifo_wr_data_0=16'h1111;//对应A
  fifo_wr_data_1=16'h2222;
  fifo_wr_data_2=16'h3333;
  fifo_wr_data_3=16'h4444;
  fifo_wr_en=4'b1111;
  packed_fifo_wr_overflow=1'b0;
 end
 
 always #10 clk=~clk;
 
 
 
endmodule

Thanks and here is my tb code.

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2024/04/09 11:49:41
// Design Name: 
// Module Name: cpack_sim
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module cpack_sim();
//input
reg clk;
reg reset;
reg enable_0;
reg enable_1;
reg enable_2;
reg enable_3;
reg [3:0] fifo_wr_en;
reg [31:0] fifo_wr_data_0;
reg [31:0] fifo_wr_data_1;
reg [31:0] fifo_wr_data_2;
reg [31:0] fifo_wr_data_3;
reg packed_fifo_wr_overflow;
//output
wire fifo_wr_overflow;
wire packed_fifo_wr_en;
wire packed_fifo_wr_sync;
wire [127:0] packed_fifo_wr_data;

design_1_wrapper u_util_cpack2
(
.enable_0 (enable_0),
.enable_1(enable_1),
.enable_2(enable_2),
.enable_3(enable_3),
.fifo_wr_data_0 (fifo_wr_data_0),
.fifo_wr_data_1 (fifo_wr_data_1),
.fifo_wr_data_2 (fifo_wr_data_2),
.fifo_wr_data_3 (fifo_wr_data_3),
.clk (clk),
.reset (reset),
.packed_fifo_wr_overflow (packed_fifo_wr_overflow),
.packed_fifo_wr_sync(packed_fifo_wr_sync),
.packed_fifo_wr_data (packed_fifo_wr_data),
.fifo_wr_overflow (fifo_wr_overflow),
.packed_fifo_wr_en (packed_fifo_wr_en),
.fifo_wr_en (fifo_wr_en)
);

initial
begin
  clk=1'b0;
  reset=1'b1;
  #200
  reset=1'b0;
  enable_0=1'b1;
  enable_1=1'b1;
  enable_2=1'b1;
  enable_3=1'b0;
  fifo_wr_data_0=16'h1111;//对应A
  fifo_wr_data_1=16'h2222;
  fifo_wr_data_2=16'h3333;
  fifo_wr_data_3=16'h4444;
  fifo_wr_en=4'b1111;
  packed_fifo_wr_overflow=1'b0;
 end
 
 always #10 clk=~clk;
 
 
 
endmodule

Thanks and here is my tb code.