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About the Channel CPACK Utility Core IP output data in the ADRV9009 ZC706 reference design

Category: Software
Product Number: 0
Software Version: 21.2

hello, I have a question about the Channel CPACK Utility Core IP output data in the ADRV9009 ZC706 reference design.I made a testbench about this ip in a new projech,which only contains this ip core.And from the scoped image below(if it's clear enough).I think the output packed_fifo_wr_data seems wrong,unlinke it's wiki introduction,it's seems to be 0000 0000 00000 0000 4444 3333 2222 1111.It is my error?Or it is the right output.My testbench only simply input the data and give a enable signal.

and I also test when 3 channels are enabled.I am not sure it is right or wrong.and it's data is 01030201 02010302 03020103 which every single number means four same numble.

Thanks,

Cai

Top Replies

  • Hi,

    We will be looking into this matter next week.

    Best regards,
    Iulia

  • `timescale 1ns / 1ps
    //////////////////////////////////////////////////////////////////////////////////
    // Company: 
    // Engineer: 
    // 
    // Create Date: 2024/04/09 11:49:41
    // Design Name: 
    // Module Name: cpack_sim
    // Project Name: 
    // Target Devices: 
    // Tool Versions: 
    // Description: 
    // 
    // Dependencies: 
    // 
    // Revision:
    // Revision 0.01 - File Created
    // Additional Comments:
    // 
    //////////////////////////////////////////////////////////////////////////////////
    
    
    module cpack_sim();
    //input
    reg clk;
    reg reset;
    reg enable_0;
    reg enable_1;
    reg enable_2;
    reg enable_3;
    reg [3:0] fifo_wr_en;
    reg [31:0] fifo_wr_data_0;
    reg [31:0] fifo_wr_data_1;
    reg [31:0] fifo_wr_data_2;
    reg [31:0] fifo_wr_data_3;
    reg packed_fifo_wr_overflow;
    //output
    wire fifo_wr_overflow;
    wire packed_fifo_wr_en;
    wire packed_fifo_wr_sync;
    wire [127:0] packed_fifo_wr_data;
    
    design_1_wrapper u_util_cpack2
    (
    .enable_0 (enable_0),
    .enable_1(enable_1),
    .enable_2(enable_2),
    .enable_3(enable_3),
    .fifo_wr_data_0 (fifo_wr_data_0),
    .fifo_wr_data_1 (fifo_wr_data_1),
    .fifo_wr_data_2 (fifo_wr_data_2),
    .fifo_wr_data_3 (fifo_wr_data_3),
    .clk (clk),
    .reset (reset),
    .packed_fifo_wr_overflow (packed_fifo_wr_overflow),
    .packed_fifo_wr_sync(packed_fifo_wr_sync),
    .packed_fifo_wr_data (packed_fifo_wr_data),
    .fifo_wr_overflow (fifo_wr_overflow),
    .packed_fifo_wr_en (packed_fifo_wr_en),
    .fifo_wr_en (fifo_wr_en)
    );
    
    initial
    begin
      clk=1'b0;
      reset=1'b1;
      #200
      reset=1'b0;
      enable_0=1'b1;
      enable_1=1'b1;
      enable_2=1'b1;
      enable_3=1'b0;
      fifo_wr_data_0=16'h1111;//对应A
      fifo_wr_data_1=16'h2222;
      fifo_wr_data_2=16'h3333;
      fifo_wr_data_3=16'h4444;
      fifo_wr_en=4'b1111;
      packed_fifo_wr_overflow=1'b0;
     end
     
     always #10 clk=~clk;
     
     
     
    endmodule
    

    Thanks and here is my tb code.

  • Hi,

    We are currently investigating this and will get back to you as soon as we have an answer.

    Thank you for your patience,
    Iulia

  • Hi  ,

    I looked into this issue and created a testbench for the CPack and the UPack instances since these are similar modules. I tested the modules in different forms by eye, and didn't seem to find an issue with them yet. I'll still have to integrate a scoreboard to make sure that all of the data is transmitted properly and everything is aligned as it should be. 

    You can find this testbench here: https://github.com/analogdevicesinc/testbenches/tree/util_pack. It is on a separate repository dedicated to IP and project verification. 

    A quick guide on how to use the testbenches repository, since we're don't have a documentation for it just yet. 
    1: Clone the Testbenches repository inside the HDL repository (HDL will contain Testbenches)
    2: Go to util_pack
    3: Run this command: make MODE=gui (this will build the project, open the Vivado gui and run the simulation as well)
    4: Check the data and other things you're interested in

    Mentions:
    You can change the configuration to whatever you want to test by going to the cfg folder under util_pack and editing the cfg1.txt file. This will give you other options on how you can set up CPack and UPack parameters for the testbench.
    Once you edit the file, you can just rerun make MODE=gui. This will rebuild the project only if the configuration file was modified. Otherwise, it'll just run the simulation. If you want to make sure you rebuild everything from scratch, so nothing is left behind, run make clean all MODE=gui. This will always clear the project and rebuild it. 

    I'll be working on the scoreboard for these modules tomorrow and get back to you with an update. 

    Regards,
    -Istvan

  • Hi Istvan,

    I truly appreciate your timely help.And I'll try the method you provided today.Besides,I check my project again,I still can't find the question out.My project's block design is as follows.

    If you have any suggestions for that or if there some questions I have never noticed?

  •  Could you help me to fix this error?It's seems like the project-sim.mk has some errors.Or just show me the waves you got

  • Hi  ,

    Before I suggest anything on this side, I'd like to help you build and open up the testbench project, as it'll help you understand the packers a little better.
    The testbench itself that you'll see is different from what you've created and it's a bit more difficult to understand. It has some extra stuff around it so it's easier to integrate it into other systems for newcomers.
    After you manage to build the project, check out the waveform, we can go further with your issue. 

    Regards,
    -Istvan

  • Hi  ,

    I check the error message you got and tried to replicate the issue on my end as well.

    The problem that you're facing is an issue that is coming from our and primarily. You see, the Testbenches repository is going with the main branch of the HDL repository and we don't really have any backwards compatibility between the two just yet. However, there's a way around this.

    Check out the main branch for HDL and update the util_pack branch in Testbenches, as I uploaded a fix a couple of minutes ago. The cpack and upack IPs were not changed for years, so both branches from HDL will have the exact same IP, no differences. 

    Use this command to prevent error generation from Vivado: export ADI_IGNORE_VERSION_CHECK=1. This will enable you to run the code with older Vivado versions. 

    Suggestion: go into the library folder, and run make clean. This will clean up all of the created IPs, so when you're trying to build anything, there will be no residual files, that can cause issues with the testbench. And when you run the testbench with the make command, it should automatically build everything for you. 

    Tested with Vivado version: 2021.1; HDL branch: main; Testbenches branch: util_pack; exported version check disabled. 

    Let me know if you're still having issues with the testbench.

    Regards,
    -Istvan

  • Hi Istvan,

    After I rename the directory from "testbenches_util-pack"to"testbenches",it works.But then it stay in this page and stuck in this.

    and my computer open vivado automatically.But just stay in its home page and won't run sim.

    Thank you again for your help.

  • Hi  ,

    If you have Vivado opened, please go to the Tcl Console, and check the logs in there to see what's happening. Sometimes Vivado doesn't throw any errors in a new window, it just doesn't run. 

    Regards,
    -Istvan