Category: Hardware
Product Number: AD9625
I'm trying to interface AD9625 with FPGA.
and i i'm currently referring to the reference design(github.com/.../fmcadc2).
in the reference design, the lane rate is set to 12.5 Gbps. But i understand that AD9625 uses 6.5 Gbps.
So my question is as below.
Q1) Is it right to change the lane rate of IP? As far as I know, AD9625 uses 6.5 Gbps.
Q2) Is it possible to operate without changing lane rate?
Q3) Is there anything else I need to change besides the lane rate of IP? For example, some clock constraint in system_const.xdc?
