I'm trying to use the ADI Transceiver Toolbox's HDL targeting to generate a custom IP design for zc706 + ad9371/ad9375 boards (by using Simulink). I just want to clarify the clock rate setting for my custom design.
As shown in the HDL workflow advisor and AD9371 reference design, the IP's Tx in and Tx out (tx_ad9371_tpl_core/dac_data_*) are all 32 bits wide. I learned that the 32bits contains two consecutive samples tx[n] and tx[n+1], where lower 16 bits are sample [n] and upper 16 bits are [n+1]. reference: https://ez.analog.com/fpga/f/q-a/51949/ad9371-why-are-dac-channels-32-bit-when-the-data-is-14-bit.
The Rx, on the other hand, are all 16bits with one sampe on each channel.
So, let's say I have the following ad9371 configuration in profile generator:
My understanding is that, when I'm designing the custom IP in Simulink, I should set all the interface clock (including Tx in&out, Rx in&out with their valid signal) to 122.88MHz. For the Tx out (tx_ad9371_tpl_core/dac_data_*), I should generate two IQ samples every clock and concatenate their bits to 32bits one as mentioned above. The Tx Out valid signal, should be considered to always be true. For the Rx input (rx_ad9371_tpl_core/adc_data_*), I should expect one sampe every clock cycle on each channel, and the Rx In valid signal always be true after the receiving starts.
So is my understanding correct? I'm looking forward to receiving any confirmation or correction.
Also, since my application requires only 32MHz TxRx with 5 times BW for DPD. I think it will be beter if I can set the Tx rate to 200MHz and Rx rate to 100MHz with a Rx BW of 40MHz (everything else stays the same). But it seems such a clock will cause problem if I still use 30.72MHz reference clock? So if such a configuration will be used, I would have to change the reference clock and maybe the VCXO onboard?
Thank you for your attention to my question!
