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SPI Engine Offload outputting extra TValid when reading AD4630-24 test pattern data.

Category: Hardware
Product Number: AD4630-24


I have an EVAL-AD4630_FMCZ connected to an AC701 Eval kit from AMD/Xilinx. I have implemented the PL design the same as in the ad4630_fmc_zed project. The only differences are I'm using a Microblaze instead of a Zynq and I've replaced the ADI DMAC with the AMD AXI DMA core. I've inserted an ILA between the data reorder block and the DMA Core and it appears that an extra TValid is being asserted when the data is clearly not ready. I tracked the TValid signal through the SPI engine cores to the execution block and I don't see how this could be happening. Let me know if you need more information.