Category: Software
Product Number: ADRV9361Z7035
Software Version: master
I'm creating a design for a carrier (based on the HDL avdrv9361z7035/ccbob_cmos project). The design has multiple custom cores with axi4 interfaces.
When connecting the axi interfaces, ad_cpu_interconnect() assigns sys_cpu_clk & sys_cpu_resetn for the interconnect. I need to use a different clock. How can I accomplish this?
Thanks,
Charlie