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How to change AXI4 clock

Category: Software
Product Number: ADRV9361Z7035
Software Version: master

I'm creating a design for a carrier (based on the HDL avdrv9361z7035/ccbob_cmos project). The design has multiple custom cores with axi4 interfaces.

When connecting the axi interfaces, ad_cpu_interconnect() assigns sys_cpu_clk & sys_cpu_resetn for the interconnect. I need to use a different clock. How can I accomplish this?

Thanks,

Charlie

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  • Hi,

    The easiest way would be the following:

    After you build the reference design, open the GUI. Disconnect and connect whatever signal you want, from GUI. In the Tcl console, you can see some commands printed. You can take those and add them in the .tcl file of the project. You will see that we write commands differently than what's printed in the Vivado Tcl console, and that's because we have some wrappers defined in https://github.com/analogdevicesinc/hdl/blob/main/projects/scripts/adi_board.tcl to make the commands look simpler and be easier to use.

    Best regards,
    Iulia

  • Thanks Lulia for the suggestion. I may find it to be  the best approach. We do have 17 cores to add :-)

    For grins, I am currently trying a different technique: I made a custom version of ad_cpu_interconnect(), where I can specify the clock and reset. The board diagram looks correct, although I haven't completed a build.

    Luckily smartconnect isn't being used at this point in the build; although I can't find where $use_smartconnect is being set to 0?

    There is a lot going on in ad_cpu_interconnect(). Do you see any reason why my approach wouldn't work?

    Thanks,

    Charlie

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  • Thanks Lulia for the suggestion. I may find it to be  the best approach. We do have 17 cores to add :-)

    For grins, I am currently trying a different technique: I made a custom version of ad_cpu_interconnect(), where I can specify the clock and reset. The board diagram looks correct, although I haven't completed a build.

    Luckily smartconnect isn't being used at this point in the build; although I can't find where $use_smartconnect is being set to 0?

    There is a lot going on in ad_cpu_interconnect(). Do you see any reason why my approach wouldn't work?

    Thanks,

    Charlie

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