Hi,
I have downloaded the TCL files from GITHUB available in the following link for building sample vivado example project for ADRV9009 ON ZC706
Releases · analogdevicesinc/hdl (github.com)
Tools used:
1.Vivado 2019.1
2.Tried in both windows and Linux environment.
Trying to implement but couldn't figure out what is the issue. These are some issues that are showing up and block design could not be generated.
Any procedure for building the block design will be helpful
P.S: We have assigned source paths wherever it is required.