AD9081
Recommended for New Designs
The AD9081 mixed signal front end (MxFE®) is a highly integrated device with four 16-bit, 12 GSPS maximum sample rate, RF digital-to-analog converter...
Datasheet
AD9081 on Analog.com
Hello,
We are trying to build HDL document, following the steps here: https://wiki.analog.com/resources/eval/user-guides/ad9081_fmca_ebz/radar
To be specific, we run the following code:
source /tools/Xilinx/Vivado/2022.1/settings64.sh # Clone the HDL git clone https://github.com/Yamakaja/hdl.git git switch data_offload # Navigate to the ad9081 / ZCU102 project cd projects/ad9081_fmca_ebz/zcu102/ # Build the project with TDD support. Note that enabling TDD support is only possible if you also enable shared device clocks, which means that your IO rates will be symmetrical. make TDD_SUPPORT=1 SHARED_DEVCLK=1
While there is an error:
Building util_cdc library [/home/pci/hdl/library/util_cdc/util_cdc_ip.log] ... OK Building util_axis_fifo library [/home/pci/hdl/library/util_axis_fifo/util_axis_fifo_ip.log] ... OK Building axi_dmac library [/home/pci/hdl/library/axi_dmac/axi_dmac_ip.log] ... OK Building axi_sysid library [/home/pci/hdl/library/axi_sysid/axi_sysid_ip.log] ... OK Building axi_tdd library [/home/pci/hdl/library/axi_tdd/axi_tdd_ip.log] ... OK Building util_axis_fifo_asym library [/home/pci/hdl/library/util_axis_fifo_asym/util_axis_fifo_asym_ip.log] ... OK Building data_offload library [/home/pci/hdl/library/data_offload/data_offload_ip.log] ... OK Building ad_ip_jesd204_tpl_adc library [/home/pci/hdl/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_ip.log] ... OK Building ad_ip_jesd204_tpl_dac library [/home/pci/hdl/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_ip.log] ... OK Building axi_jesd204_common library [/home/pci/hdl/library/jesd204/axi_jesd204_common/axi_jesd204_common_ip.log] ... OK Building axi_jesd204_rx library [/home/pci/hdl/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ip.log] ... OK Building axi_jesd204_tx library [/home/pci/hdl/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ip.log] ... OK Building jesd204_common library [/home/pci/hdl/library/jesd204/jesd204_common/jesd204_common_ip.log] ... OK Building jesd204_rx library [/home/pci/hdl/library/jesd204/jesd204_rx/jesd204_rx_ip.log] ... OK Building jesd204_tx library [/home/pci/hdl/library/jesd204/jesd204_tx/jesd204_tx_ip.log] ... OK Building jesd204_versal_gt_adapter_rx library [/home/pci/hdl/library/jesd204/jesd204_versal_gt_adapter_rx/jesd204_versal_gt_adapter_rx_ip.log] ... OK Building jesd204_versal_gt_adapter_tx library [/home/pci/hdl/library/jesd204/jesd204_versal_gt_adapter_tx/jesd204_versal_gt_adapter_tx_ip.log] ... OK Building sysid_rom library [/home/pci/hdl/library/sysid_rom/sysid_rom_ip.log] ... OK Building util_adcfifo library [/home/pci/hdl/library/util_adcfifo/util_adcfifo_ip.log] ... OK Building util_dacfifo library [/home/pci/hdl/library/util_dacfifo/util_dacfifo_ip.log] ... OK Building util_fifo2axi_bridge library [/home/pci/hdl/library/util_fifo2axi_bridge/util_fifo2axi_bridge_ip.log] ... OK Building util_cpack2 library [/home/pci/hdl/library/util_pack/util_cpack2/util_cpack2_ip.log] ... OK Building util_upack2 library [/home/pci/hdl/library/util_pack/util_upack2/util_upack2_ip.log] ... OK Building util_tdd_sync library [/home/pci/hdl/library/util_tdd_sync/util_tdd_sync_ip.log] ... OK Building interface definitions [/home/pci/hdl/library/interfaces/interfaces_ip.log] ... OK Building axi_adxcvr library [/home/pci/hdl/library/xilinx/axi_adxcvr/axi_adxcvr_ip.log] ... OK Building util_adxcvr library [/home/pci/hdl/library/xilinx/util_adxcvr/util_adxcvr_ip.log] ... OK Building ad9081_fmca_ebz_zcu102 project [/home/pci/hdl/projects/ad9081_fmca_ebz/zcu102/ad9081_fmca_ebz_zcu102_vivado.log] ... FAILED For details see /home/pci/hdl/projects/ad9081_fmca_ebz/zcu102/ad9081_fmca_ebz_zcu102_vivado.log make: *** [../../scripts/project-xilinx.mk:65: ad9081_fmca_ebz_zcu102.sdk/system_top.xsa] Error 1
Please refer the attached file for the detailed error log
2678.ad9081_fmca_ebz_zcu102_vivado.log
The Vivado version we used is 2022.1. Could you help us with this problem?
Best,
Dongyu
travisfcollins - Moved from Microcontroller no-OS Drivers to FPGA Reference Designs. Post date updated from Tuesday, February 20, 2024 9:09 PM UTC to Tuesday, February 20, 2024 9:59 PM UTC to reflect the move.
travisfcollins - Moved from Microcontroller no-OS Drivers to FPGA Reference Designs. Post date updated from Tuesday, February 20, 2024 9:59 PM UTC to Tuesday, February 20, 2024 9:59 PM UTC to reflect the move.
Hi Dongyu
This is Ivan, thank you for reaching out and bringing the matter to our attention. I have received your inquiry and am currently looking into the issue. I will get back at you as soon as possible.
Regards,
Ivan
Hi Dongyu ,
Could you try building this project from the main branch? I will update the documentation to reflect this change. Thanks for bringing it up.
These extra changes that were on that fork, have been merged already into the main branch.
Our main branch uses Vivado 2023.2, is there any chance you could update your Vivado version?
Best regards,
Iulia
Hi lulia,
Thanks for your reply! After I reset the license, I can run it successfully! Thanks again!
Dongyu