prbs generator and checker verilog or vhdl code for testing of JESD204B interface

Question

Hi, 
 In my design use the ADRV9009 that connected to FPGA. 
 I want to check the Data interface - JESD204B: TX (de framer) and RX (framer). 
 Do you have the VERILOG or VHDL code that implement the PRBS generator PN7,9 or other? and checker PN7,9 or other? 
 Thanks Haim

iulia · Accepted Answer

https://github.com/analogdevicesinc/hdl/blob/main/library/common/ad_pngen.v)

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prbs generator and checker verilog or vhdl code for testing of JESD204B interface

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