Post Go back to editing

prbs generator and checker verilog or vhdl code for testing of JESD204B interface

Category: Hardware
Product Number: ADRV9009


In my design use the ADRV9009 that connected to FPGA.

I want to check the Data interface - JESD204B: TX (de framer) and RX (framer).

Do you have the VERILOG or VHDL code that implement the PRBS generator PN7,9 or other? and checker PN7,9 or other?


Thread Notes

Parents Reply Children