Data being cutoff; or am I not formatting correctly?

I assume you have a custom IP of a QPSK modulator?  When you simulate this IP what is the scale of its output data?

-Travis

The output data is (1,16,14) which is signed 16 with 14 decimal places. The input data is uint16. Im basically trying to make this portion in gnuradio, Thie picture doesnt have the correct values because Simulink is trolling me at the moment and wont let me compile the design again.


I think that's what you mean. I know that the char to complex block allows me to set a scale of 32767, but I dont see how I could integrate that into this.

Beauxrel said:

(1,16,14)

You are connecting this to a port that needs an int16. How is the implementation mapping values?

-Travis

I updated the picture, basically it grabs the constellations upsamples by 4 and then sends it the hardware through the I and Q inputs within the IP core the 1s and 0s are unpacked and modulated, lastly sent through a hardware pulse shaper. and then output to the fifo.

These are doubles... This is what you put in the FPGA?

-Travis

No, the doubles are Simulink being weird. What comes in are uint16 and what comes out are the fixed values that get fed to the fifo. Its to my understanding that this example works off of the brilliant adi hdl reference design. And I hope that is what GNURadio is doing as well, it seems to know what to do when we modulate outside of the fpga.

I would recommend explicitly casting to int16 ports.

-Travis

are you saying both input and output should be cast to int16? I understand the input because those are just 1 and 0. But the ouput would be pulsed shaped qpsk constellations i.e(signed fixed point values) Is the DAC FIFO not able to read signed fixed value points?

Beauxrel said:

are you saying both input and output should be cast to int16?

This is what the source (From DMA) and sink (to FIFO) expect. It really shouldn't matter on the source between uint16 and int16 as long as you don't exceed 15 bits.

Beauxrel said:

Is the DAC FIFO not able to read signed fixed value points?

The connected port is a 16 bit interface.  What does fi(1,16,14) actually resolve to in generated code?

-Travis

 output  signed [15:0] int16_src_RRC_Interpolation_Filter_out_re; //sfix16_En14