I'm considering using the CLK_OUT output from an AD9363 in an FPGA design but I'm not sure how to constrain it in my SDC file. Is there a phase relationship between this clock and the DATA_CLK output accompanying the receive data bus? Can I assume some sort of fixed phase relationship or do I need to treat them as having an arbitrary phase offset and use a small FIFO to pass data from one domain to the other?
Just as some background, I was trying to use the reference design for the AD9361 to configure the data interface but I needed to add an extra PLL to create a divided-down version of the clock; this is a modification of an existing design and I don't have an extra PLL on the same side of the FPGA to use, so Quartus was unable to fit the design in the part (Cyclone V if that matters). I was thinking it might be convenient to use the CLK_OUT output to create this divided-down clock, but I need it to be in the same clock group, so I need to know the phase relationship between it and DATA_CLK so I can configure the virtual clocks in the SDC file accordingly.
