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fft on analog devices reference designs

Category: Hardware

hello , i'm interest of implementing and fft ip core in the usrp312 ref design (and also on the ad9361 -7z035 design) .

assuming that the fft block provided in vivado have axi interface and not regular interface how would you connect the ip core to the reference design in the rx chain ?

  • Hi,

    Unfortunately, we cannot provide support for the Xilinx FFT IP, since it was not made by ADI.
    However, maybe I can give you a few pointers: the regular FIFO-style interface used for those ad9361 designs does not support backpressure like the AXI-Stream interface that the Xilinx IP requires. So, you have to handle this yourself, and it really is case dependent. If you are using that IP in a configuration such that it doesn't need any backpressure, you might be able to simply ignore the 'tready' signal. Otherwise, you may need to buffer the samples in a FIFO, and find a way to guarantee that it won't overflow (that the FFT throughput is enough to consume the incoming samples even with the gaps in processing).

    - Laez