Hello,
I've been looking at the ADRV9009 reference designs featuring multiple ADRV9009s, and have a question regarding their usage of SYSREF:
Generally, in the system block diagrams, three independant sysref ports are connected to RX , ORX and TX JESD modules... and on the top level, ORX and TX share the same SYSREF , associated with one device, while the RX module gets a SYSREF associated to another device.
On a design where multiple ADRV9009s are all locked to the same reference, is there any benefit/requirement of getting multiple SYSREF to the FPGA ?
My understanding is that we should only require 1 reference clock and 1 sysref going to the FPGA, in order to synchronize multiple ADRV9009s, and thus use that single SYSREF on RX,TX and ORX JESD modules. Is that correct ?
Thank you.
Best regards,
Romain
