Hey,
I've cloned the hdl_2019_r1 branch (https://github.com/analogdevicesinc/hdl/tree/hdl_2019_r1) from which I want to build the reference design for the ADRV9364-Z7020 on a Windows machine that has Vivado 2019.1 on it.
I tried to follow this guide:
https://wiki.analog.com/resources/fpga/docs/build#:~:text=projects/daq2/zc706.-,Xilinx%20auto%20Tcl%20build,-We%20do%20not
As much as I understand - I need to build the required ADI libraries prior to build the project of the ADRV9364 itself, So:
I navigated to the ADRV9364-Z7020 folder (actually to the CCBOB_CMOS project in this folder) and tried to run the following in the tcl console in Vivado:
1.
source ../../scripts/adi_make.tcl
2.
adi_make::lib all
1 seem to work fine (no errors)
but when I run 2 - it does recognize which libraries it should build but I'm getting the following error:
WARNING: [IP_Flow 19-1971] File named "../xilinx/common/up_xfer_cntrl_constr.xdc" already exists in file group "xilinx_anylanguagesynthesis", cannot add it again.
ERROR: [Common 17-39] 'ipx::reorder_files' failed due to earlier errors.
while executing
"ipx::reorder_files -front $i_file $i_filegroup"
("foreach" body line 7)
invoked from within
"foreach i_file $ip_constr_files {
set i_module [file tail $i_file]
regsub {_constr\.xdc} $i_module {} i_module
ipx::add_file $i_file $i_fi..."
(procedure "adi_ip_properties_lite" line 32)
invoked from within
"adi_ip_properties_lite $ip_name"
(procedure "adi_ip_properties" line 3)
invoked from within
"adi_ip_properties axi_ad9361"
(file "C:/t/adi_hdl/hdl-2019_r1/library/axi_ad9361/axi_ad9361_ip.tcl" line 53)
INFO: [Common 17-206] Exiting Vivado at Wed Sep 20 00:19:43 2023...
ERROR: [IP_Flow 19-851] Cannot find !C:\t\adi_hdl\hdl-2019_r1\library\xilinx\common\up_xfer_cntrl_constr.xdc1! to reorder: "(null)".ÿ
I checked and there is a file named "up_xfer_cntrl_constr.xdc" under the path mentioned in the error message....
Can someone help me here please ?
