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Sharing util_adxcvr_v1 between two AD9375 devices

Category: Hardware
Product Number: AD9375
Software Version: 2021_R2


I have a requirement to connect two AD9375 devices to a Xilinx Ultrascale+ FPGA. I only have access to a single QUAD on the FPGA - so four GTH transceivers and one GTH common. For each AD9375, I only require the following number of lanes:
TX = 1 lane

RX = 1 lane

Obs RX = 1 lane

So I can fit a single AD9375 into two lanes and hence two AD9375s into four lanes. Both AD9375 devices will run at the same sample rates and use the same reference clocks from a common clock source.

I have built the ADI reference design for the ADRV9371 evaluation board on the ZCU102. I can see how the JESD204B blocks interact in the Block Design. Currently all the components are configured for 4 lanes per device. Obviously the ADRV9375 evaluation board only has a single AD9375 device on it. But I would like to use the ADI reference design as a firmware starting point for my custom hardware which will have two AD9375 devices on.

My question is as follows:

To modify the reference firmware design to add a second AD9375 into a single FPGA QUAD should I:

1) Change the configuration of all existing blocks to only use two lanes total (2 for TX, 1 for Rx, 1 for Obs RX), and then DUPLICATE all firmware blocks to achieve two AD9375 devices with four lanes in total.


2) Are there firmware blocks that can be SHARED between two AD9375 devices since they will be running at the same sample rate from the same clock source? For example, can I leave util_adxcvr_v1 configured for 4 lanes and connect two of the lanes to the ADI JESD blocks of the first AD9375 device and the other two lanes to the ADI JESD blocks of the second AD9375 device?

Normally, I would have just done option (1) and duplicated everything. The problem with this approach is that I only have a single FPGA QUAD available and, as such, only a single GTH common available. It appears as if util_adxcvr_v1 uses the GTH common of the quad so I wouldn't be able to add a second util_adxcvr_v1 without there being contention for the shared GTH common.

I am using HDL reference branch 2021_R2 as my starting point.

I hope what I am asking is making sense. Please let me know what you think.



  • OK, I think I have answered my own question. I built the ADI HDL reference design adrv9009zu11eg. This is for the ADI ZU11EG SOM with two ADRV9009 devices on. I opened the project in Vivado and I see that there are only one complete set of all the JESD components. These components are configured to be wide enough to support both ADRV9009 devices. In other words, the each JESD component handles the data from both ADRV9009 devices.

    So in my case I can start with the ADI reference design for a single AD9371 device which is four lanes wide. I can then use this firmware to connect to two AD9371 devices configured for only two lanes each. I will need to make a few minor modifications in the top level firmware. For example, the RX SYNC will need to be duplicated to go to the RX SYNC of both AD9371 devices and the TX SYNC will be the AND of the TX SYNC signals received from both AD9371 devices.

    Based on the adrv9009zu11eg example design, I believe I can apply the same theory of operation here. It would be nice if I can get confirmation from an ADI representative that it is OK to proceed with this plan for two AD9371 devices.


  • Hello,

    Apologies for the late reply. You are right in your approach, but I would recommend also looking at the fmcomms8 as an example, since it is an evaluation board used with the ZCU102 that does the same for two ADRV9009 devices, while the adrv9009zu11eg is a SOM.

    Best regards,