AD9361 No-OS custom board with a10 fpga, TX tuning failed

Hi,

Ideally the delay for data and frame in regards to the tx clock should be close to none. The tuning algorithm should set the right delays at the ad9361 level.
Can you add a signal tap and look at the signals? Is there something strange on the tx side. 
I would suggest to double check the hardware connections as much as possible on the tx.
- are data/frame pins connected correctly?
- do you have test points on the FMC doughtier card or an extender/expansion card that word allow you access to the clock/frame/data lines for debug?

Andrei

Hi,

I added a few clk_buffers at rx_clk, after that ad9361 is tuning at 25 MHz for both RX and TX but failing for both 40MHz and 61.44MHz.

I just want to point out that this is the case with a10 and ad9361. So Altera serdes IP is used and that too in non-dpa mode. 

Maybe individual serdes elements (one for each tx_data_out[0..5]) are adding variable delays, due to which ad9361 is not tuning at higher data rates?

Would request your comments on this issue.

Regards

Prince

Hi,

I will have to think/consult with colleagues about this, mostly in regards with the a10 SERDES, haven't played with it in a while. From the top of my head, this should not be the case on tx, but maybe I'm missing something.

Andrei

Hi,

Some hardware things that can cause this behavior:
1. trace length mismatch
2. cross talk between clock and data/frame lines.
My suggestion is to check the above and play a bit with the drive strength of the tx pins.

Andrei

Hi Andrei,

Just a quick query about trace length. should the tx data lines and rx data lines have same trace length? 

I mean frame lines, data lines etc should all have same trace length?

Regards

Prince

Hi,


Yes, as a group, on Rx clock, frame and data should have the same trace lengths, similar for the Tx group. The interfaces are source synchronous, making Tx and Rx lines at the same trace length does not add any benefit from my point of view.

Andrei