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AD9361 No-OS custom board with a10 fpga, TX tuning failed

Product Number: AD9361
Software Version: Quartus 18.1


I am trying to calibrate AD9361 on a custom board with A10 FPGA. 

For initial setup, In RX mode AD9361 is tuning for 25MHz and 40MHz but not for 61.44MHz

TX is not at all tuning

What might be the reason for this error.



Parents Reply
  • Hi,

    I added a few clk_buffers at rx_clk, after that ad9361 is tuning at 25 MHz for both RX and TX but failing for both 40MHz and 61.44MHz.

    I just want to point out that this is the case with a10 and ad9361. So Altera serdes IP is used and that too in non-dpa mode. 

    Maybe individual serdes elements (one for each tx_data_out[0..5]) are adding variable delays, due to which ad9361 is not tuning at higher data rates?

    Would request your comments on this issue.