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AD9361 No-OS custom board with a10 fpga, TX tuning failed

Product Number: AD9361
Software Version: Quartus 18.1


I am trying to calibrate AD9361 on a custom board with A10 FPGA. 

For initial setup, In RX mode AD9361 is tuning for 25MHz and 40MHz but not for 61.44MHz

TX is not at all tuning

What might be the reason for this error.



Parents Reply
  • Hi,

    Sorry for the delay.

    Does executing intel_serdes in non-dpa mode, affects the digital tuning of ad9361?

    Active DPA helps. Ideally you wil control the PLL feeding the DPA at run time. If you create the proper constraints regarding the delays between data lines and clock, you should be fine.

    Also which is the best suitable hdl repository for A10+AD9361

    We always recommend the latest release or master branch, because we have the tools installed and have a good knowledge of the features/fixes/limitations/bugs.
    But in this case, we do not have an active design supported on a10 with AD9361, and the last functional changes done on axi_ad9361 for a10 were included in hdl_2019_r2 branch.

    You decide what version is better suited for you. The support we ca offer is limited in this case.