Hi,
I am trying to calibrate AD9361 on a custom board with A10 FPGA.
For initial setup, In RX mode AD9361 is tuning for 25MHz and 40MHz but not for 61.44MHz
TX is not at all tuning
What might be the reason for this error.
Thanks
Prince
AD9361
Recommended for New Designs
The AD9361 is a high performance, highly integrated radio
frequency (RF) Agile Transceiverâ„¢ designed for use in 3G and
4G base station applications....
Datasheet
AD9361 on Analog.com
Hi,
I am trying to calibrate AD9361 on a custom board with A10 FPGA.
For initial setup, In RX mode AD9361 is tuning for 25MHz and 40MHz but not for 61.44MHz
TX is not at all tuning
What might be the reason for this error.
Thanks
Prince
let me know if more clarification is required
Are you using CMOS or LVDS interface?
Also, are you using the latest no-OS drivers? If not using latest, then please upgrade to the latest and then try initializing with the default sequence:
https://github.com/analogdevicesinc/no-OS/tree/master/projects/ad9361
https://github.com/analogdevicesinc/no-OS/tree/master/drivers/rf-transceiver/ad9361
https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/software/baremetal#downloads
Hi srimoyi
I am using LVDS interface
As for the hdl, I am using hdl_2019R1, for its compatibility with Quartus 18.1 std.
Does executing intel_serdes in non-dpa mode, affects the digital tuning of ad9361?
Also which is the best suitable hdl repository for A10+AD9361
Moving to FPGA reference designs for comments.
Moving to FPGA reference designs for comments.
Hi,
there is one more observation in the design, if we try to calibrate it at LO > 3 GHz, it throws error ”Failed to restore ensm state”
there is one more observation in the design, if we try to calibrate it at LO > 3 GHz, it throws error ”Failed to restore ensm state”
Can you open a new thread regarding this on the no-OS/Linux forum?
Andrei