I'm using the ADRV9009 reference design for my project and we added some custom DMACs into the block design. Those DMACs are connected to a SXX_AXI Interface into the AXI SmartConnect (see image below). Since we added those DMACs into the project, we are not anymore able to update the ADRV9009 profile:
Does anyone have tried to used this reference design with adding some custom DMACs to the Block Design?
Can I shared the resources of one ADRV9009 DMAC and one custom DMAC into the same SmartConnect?
If yes, Do I have to split the memory address range for those input Interface in the FPGA project or the software will handle this?
Any information, details and Linux examples would be greatly appreciated.
Thanks in advance for all support you guys provided