Baremetal access of matlab generated bitstream

It really depends on the origin of the bitstream. If you used Transceiver Toolbox, yes the bitstream and drivers are designed to work together out of the box. If you used Xilinx Zynq SDR support package you will likely need to map the drivers to the relevant memory locations. The reference design from the Xilinx Zynq SDR support package is supported by MathWorks directly.

-Travis

It really depends on the origin of the bitstream. If you used Transceiver Toolbox, yes the bitstream and drivers are designed to work together out of the box. If you used Xilinx Zynq SDR support package you will likely need to map the drivers to the relevant memory locations. The reference design from the Xilinx Zynq SDR support package is supported by MathWorks directly.

-Travis

Yes I used Xilinx ZynqSDR package and the generated vivado project contains Axi Lite and IPs like bypasstx and bypassrx. I need help to access axi drivers in it.

You will need to contact MathWorks since those IPs are not authored by ADI. ADI doesn't have the source, regmaps, or doc on those components.

-Travis