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LTC2387-16 / ADAQ23875 two lane mode cnv signal polarity

Category: Datasheet/Specs
Product Number: LTC2387-16 / ADAQ23875
Software Version: Vivado 2022.2

Hi,

I am working on a small proof of concept project using ADAQ23875 eval board + zedboard (connected over FMC).

For the data acquisition the axi_ltc23875 ip core is used (from demo project cn0577)

The data transfer somehow buggy and the transferred test pattern is 0x30fc, which is actually a 2 bit shifted 0xcc3f (the right pattern according the datasheet).

I have been spent lot of time do far, for adjusting the timing parameters without any success.

The only interesting point that is fount that the CNV+/- signal should have a opposite polarity (?!) in the two lane mode (ADAQ23875 datasheet, page 21),

but I couldn't find any detailed information on this topic.

Could you guys confirm that the datasheet is OK, and the CNV signal should have opposite polarity in the two-lane mode?

Thanks,

Best Regards, Szilárd

Hi loszi,

I'm going to move your question over to our FPGA community forum.  

  • Hi Brandon,

    thank you for the relocation.

    Regards, Szilard

  • Hi Szilard,

    Our HDL has by default the 18-bit configuration. See here in the code and here in the readme.md mentioning only the 18-bit part

    Still, if you change that parameter to have the value 16, it should work.

    Let me know what's the status of this afterwards.

    Regards,
    Iulia

  • The only interesting point that is fount that the CNV+/- signal should have a opposite polarity (?!) in the two lane mode (ADAQ23875 datasheet, page 21),

    Hmm, it looks like it may be an error there. I will check into it and I'll update you as soon as I have an answer.

  • Hi Lulia,

    Thanks for the response! the ADC resolution was the first parameter that I changed.. Slight smile
    I have also added a XOR gate for changing the CNV signal polarity on the fly without to much success:

    Regards, Szilárd

  • Got the answer from the documentation team and yes, it's a typo. So no need for the XOR gate.

    I will test it on my side too and I'll come back with an answer most likely tomorrow.

    Best regards,
    Iulia

  • Dear Lulia,

    Thank you for the feedback regarding the documentation, and for your effort to test the core in 16 bit mode.

    Best wishes, Szilárd

  • Just wanted to let you know that I'm still on this issue and I'm debugging currently. I will tell you as soon as I have some news.

    iulia

  • Dear Iulia,

    thank you for your effort, and please let me know, if I can help your tests somehow.

    Best Regards, Szilárd

  • Hi Szilárd,

    Could you please try with these changes? Pay attention to the ones in bold. These need to be written in hdl/projects/cn0577/common/cn0577_bd.tcl

    ad_ip_parameter axi_ltc2387 CONFIG.ADC_RES 16
    ad_ip_parameter axi_ltc2387 CONFIG.OUT_RES 16

    ad_ip_instance axi_pwm_gen axi_pwm_gen
    ad_ip_parameter axi_pwm_gen CONFIG.N_PWMS 2
    ad_ip_parameter axi_pwm_gen CONFIG.PULSE_0_PERIOD 8
    ad_ip_parameter axi_pwm_gen CONFIG.PULSE_0_WIDTH 1
    ad_ip_parameter axi_pwm_gen CONFIG.PULSE_0_OFFSET 0
    ad_ip_parameter axi_pwm_gen CONFIG.PULSE_1_PERIOD 8
    ad_ip_parameter axi_pwm_gen CONFIG.PULSE_1_WIDTH 4
    ad_ip_parameter axi_pwm_gen CONFIG.PULSE_1_OFFSET 0

    It should be working now.

    Best regards,
    Iulia