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TransceiverToolbox Target Frequency of Reference Designs is always 0

Hi,

when using the Reference Designs within HDL Coder for IP Core integration the Target Frequncy of my design is 0 MHz always. How can I fix this?

According to MATLAB/Simulink docu a Target Frequency can be set within the HDL Workflow Advisor if additional args in hRD.addClockInterface are provided.

Best Regards, Dirk

  • Hi  ,

    Sorry for the late answer. We're looking into this issue. 

    I'd like to ask you what is the reference design that you're trying to work on, and where did you find out that the Target Frequency is 0 MHz?

    The function hRD.addClockInterface is used to connect the clock and reset signals of the Custom Matlab IP to an already existing clock and reset port, that comes from the HDL reference design. This is used when the HDL Workflow Advisor is integrating the Matlab IP into the already created reference design. You can find the specified function being used in add_clocks.m file, where the clocks and resets are connected to various modules, depending on the chosen project and design. 

    Best regards
    - Istvan

  • Hi Istvan,

    thanks for the reply.

    This happens for every Reference Design coming with the Transceiver Toolbox (e. g. "AnalogDevices ADRV9361-Z7035". But this is not the case for the Mathworks' reference desings (e. g. "ADI RF SOM").

    The difference seems to be the missing target frequency related additional option (e. g. "DefaultFrequencyMHz") when calling addClockInterface() within the Transceiver Toolbox.

    I am using Transceiver Toolbox with MATLAB/Simulink R2022b.

    Best Regards.

  • We're using Matlab R2021b version for the builds. I don't know if there are any incompatibilities or not between Matlab or Vivado.

    Can you tell us what have you done that you got to this problem? If it is the case, can you link the guide(s) that you followed building the projects? 

    - Istvan

  • I am using HDL Workflow Advisor with Reference Designs from Transceiver Toolbox. Simply the Set Target Frequency task is missing due to the missing additional option in the hRD object, as I mentionend in my previous post. Thus the Target Frequency is set to 0 MHz.


    According MathWorks' doc archives for R2021b this behaviour should be present in R2021b either.

  • The reference designs between the MathWorks authored design in "Xilinx Zynq Based Radio" and Transceiver Toolbox are a bit different. Transceiver Toolbox will rely upon the default constraints within the design while MathWorks introduce an additional constraint at the FIFOs based on that input. Transceiver Toolbox for that design will use a rate of 61.44MSPS at that position.

    Due to how HDL Workflow Advisor (HWA) works (At least I have not found a workaround) you cannot set these clock frequencies from the addClockInterface from the user level. You would need to edit the plugin_rd file each time. HWA enumerates the plugin files at initialization and not when users go through the steps.

    My understanding is that the "Xilinx Zynq Based Radio" accomplishes the clock constraint injection by using the AddParameter feature of the ReferenceDesign objects to configure this constraint through a custom IP in their block design. If you want to add a similar constraint there are a few options:

    1. Edit the constraint in the base reference design itself. Its right here: hdl/adrv9361z7035_constr_lvds.xdc at hdl_2019_r2 · analogdevicesinc/hdl · GitHub Which in inside the vivado folder within the toolbox itself

    2. Edit the constraint after the project is built in Vivado after the fact

    3. Leverage the custom script hooks to update the reference design based on MATLAB configuration. This would require creating a custom reference design plugin file similar to the Fast Frequency Hopping demo: TransceiverToolbox/trx_examples/targeting/frequency-hopping at master · analogdevicesinc/TransceiverToolbox · GitHub  You can see that the FFH demo adds a parameter to run a script with additional tcl commands to update the reference design before inserting the MATLAB generate IP: TransceiverToolbox/plugin_rd.m at master · analogdevicesinc/TransceiverToolbox · GitHub TCL script: TransceiverToolbox/fh_preprocess.tcl at master · analogdevicesinc/TransceiverToolbox · GitHub

    -Travis

  • Hi travis,

    thanks for your reply.

    Your answer refers to the synthesis/implementation, right?

    But the target frequency setting also affects the RTL Code/IP Core Generation with HWA. In my case when using HDL Coder Optimizations like Adaptive Pipelining.

    Best Regards

    Dirk

  • I’m not totally sure setting the clock will really help those optimization but feel free to simply change the max clock to 61.44 MSPS within the addclockinterface function. The code is open so you can modify it if necessary.

    -Travis

  • The optimizations really work.

    MathWorks' docu says:

    To determine the optimal number of pipeline registers to insert in your design, the optimization considers the target device, target frequency, multiplier word lengths, and the settings in the HDL Block Properties.

     

    Currently I splitted the workflow generating just the IP Core for the target device (and a target frequency for Adaptive Pipelining) and insert the IP Core in ADI's HDL Reference Designs manually. But I will consider modifying the Transceiver Toolbox as you suggested.

    Best Regards, Dirk