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How to integrate ethernet IP in the adrv9361z7035 hdl reference design. I have tried to make it recieve the i/q signals from adc fifo and rest of the connections are made via auto connection. However, upon generating the bit stream, it is giving errors

Category: Software
Product Number: adr v9361z7035 inteface with axi ethernet subsystem IP in vivado

It is giving the following errors. Kindly guide me how can I make this ethernet IP recieve the IQ signals from adc fifo and then transmit it via output port. 

I shall be highly grateful for your help. 

  • Hello,

    Thread started here:  how to record IQ signals using ad9361z7035 

    Did you do any changes to the axi_ad9361 IP? 

    Regarding the errors you're receiving, they're stating that there is no IDELAYCTRL and you used I/ODELAYs in your design, so based on this I'm guessing you changed the IP or some parameters for it.

    Depending on where you want to make the tuning, you should add an IDELAYCTRL where it's needed, for tuning on the side of the FPGA. If you don't want to use IODELAYs, then you should tune the digital interface on the side of the chip, meaning that you have to write some registers in its register map to add some delays from there.

    This being said, where do you want to make the tuning?

    Best regards,

  • Sorry for the confusion, the tuning is done by the software driver in this case.

    After analyzing more thoroughly, I see you have unconnected ports (IDATAIN and some others) to your IDELAY instance from the Ethernet IP. You should see about those.

    As next step, I suggest you to put this parameter DAC_IODELAY_ENABLE on 0 and add this line too to disable the insertion of the IDELAYCTRL modules: ad_ip_parameter axi_ad9361 CONFIG.IODELAY_CTRL 0 and build again after you've done these changes and let's see.

    Best regards,

  • yes I have changed the ad9361 reference design by adding an ethernet IP in front of the adc fifo. I want to make the reception of the i/q signals from adc by ethernet IP and then output it via ethernet external port.

    I can not say if its in built system delays, as per my design is concerned I have not added any io delay to the system. I have only added an ethernet IP and a concatenate block that can give two 16 bit data streams from adc fifo as a 32 bit data stream to the ethernet IP. 

    one more confusion that I want to clear is that, there are two signals at the output of Ethernet IP by the name of m_axis_rxd_tdata and m_axis_rxs_tdata, are these my outputs? 

    For your convenioence I have attatched the screenshot of the IP.  I am taking the input at s_axis_txc_tdata from adc fifo via concatenate block. 

    I shal;l appreciate if you will help me in this. Thank you!

  • Hello,

    I notice now in you're path that you're using hdl_2019_r2 branch, right? If so, I recommend you to use (if you can) either the master branch or hdl_2021_r1, since it's a pretty old release branch; together with this, you should change your Vivado version too, to 2022.2 or 2021.2. 

    I see you've instantiated AXI 1G/2.5G Ethernet Subsystem (axi_ethernet) in your design. I encourage you to disable the I/ODELAYs as I stated in my previous answer, to remove some of the errors you're encountering, and then check on the Xilinx forum and the Xilinx PG138 on how to use this IP. We can't offer support regarding this. Also, I think it needs a license that you have to purchase from them.

    If you don't want to pursue the scenario I stated above, then take a look at our CN0506 project, with the configuration mode GMII to RGMII; see the diagram from the previous link for more details on how it's working. You can do it similarly/adapt it in your adrv9361z7035 project. Also, this doesn't require a license.

    Best regards,

  • Hello  ,

    Do you have any updates?


  • Hey lulia! Thanks for showing concern! I am right now unable to use the other version of vivado except 20190.1. However, I have gone through the cno506 project that you have mentioned. But m noty getting how can i use it for 1d9361z7035. Can u please elaborate it!

    Huge regards

    Tanzeela iRshad.

  • Hello,

    It connects to PS7 and uses the Ethernet PHY. You should mimic the configuration for GMII to RGMII that's done in CN0506 and most likely adapt it to your needs afterwards. 


  • hey  ! I have been working on the problem since quite long. Luckily I have found a solution with adr9361-z035 FMC carrier. It has two ethernet ports. One is on  the PS side while the other is on the PL side.


    The connections of Ethernet 2 are described in the screenshot (taken from the mentioned adrv1crr-FMC datasheet). I want to make the connections as described in its  datasheet which shows  that I may access M2 port for data transfer from PL VIA GMII to RGMII IP inserted in the FPGA reference design . Its connection in the hdl reference design can be seen as follows. 

    Now I need help in doing two things. 

    1) Is it the correct way to enable the PL ethernet 2 port M2.

    2) If the above configuration is correct then I need to transfer channel 0 (I0/Q0) two 16 bit signals (I/Q) from adc fifo  via the ethernet 2 M2 to PC.?