Suitable Clock in HDL Reference Design for AD9361 z 7035

Question

Hello, 
 
 I need to design a logic to generates data bits on a data rate of 19.2Kbps, for this purpose I need to generate a clock of 19.2Khz to pick one bit at each positive edge, In HDL Reference design I am using Zynq 100Mhz clock to generate a slower clock but since 19.2K is not a multiple of 100Mhz so there comes some synchronization issues. I tried to use Sample clock of 61440000 since its a multiple of 19.2K but it is not a stable clock and I get irregular number of samples when I check it on ILA. Please suggest which source clock is stable to be used. 
 Regards

iulia · Accepted Answer

Hello, 
 In general, when you want to analyze data, you should use the same clock as the one which it came with. Otherwise you will have timing constraints violations. An alternative to this is to use a FIFO to handle the clock domain crossing, but this complicates our discussion for now. 
 See from this thread RE: How to achieve low sample rate with AD9361 ? that the min. sampling rate of AD9361 is 520Ksps. So what you're trying to achieve with capturing data at max. sample rate (61.44Msps) and then keeping just a few of them (lowering it to Ksps) doesn't really make sense for us. If you could elaborate on this matter, it would be great. 
 Regards, Iulia)

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Suitable Clock in HDL Reference Design for AD9361 z 7035