Suitable Clock in HDL Reference Design for AD9361 z 7035

Hello,

What do you want to achieve with the data? It's not very clear to me. 

Also, what clock are you using for ILA?

Regards,
Iulia

 iulia  I want to generate a generic clock to acheive data rates such as 19.2k, 7.68K and 3.84K , I tried it using 100Mhz clock , but since these rates are not exactly divisible on 100Mhz so exact rates are not generated. For this purpose I needed 61.44Mhz clock. I used div clock but when I visualized results  it on ILA the genrated clocks were not corrected since div clock wasn't stable I guess. So my question is which clock from reference design will be suitable to genrate exact clock rate

Hello,

In general, when you want to analyze data, you should use the same clock as the one which it came with. Otherwise you will have timing constraints violations. An alternative to this is to use a FIFO to handle the clock domain crossing, but this complicates our discussion for now.

See from this thread  RE: How to achieve low sample rate with AD9361 ?  that the min. sampling rate of AD9361 is 520Ksps. So what you're trying to achieve with capturing data at max. sample rate (61.44Msps) and then keeping just a few of them (lowering it to Ksps) doesn't really make sense for us. If you could elaborate on this matter, it would be great.

Regards,
Iulia

Hello Chercheur ,

Do you have any updates?

Regards,
Iulia

Closed due to inactivity